Saurin Shah — Software Engineer

A highly experienced and results-driven professional with multiple years of expertise in Static Timing Analysis (STA), Synthesis VLSI (Physical & STA Design Engineer) - Demonstrated proficiency in timing closure, clock tree building, DCD & MPW fixing, and driving cross-functional team collaboration in a world-class CPU development environment. - Strong communicator and leader, guiding teams to independently achieve complex tasks, and ensuring high-quality deliverables in mobile, computing, and automotive chip designs. - Proficient in the latest cutting-edge technologies (n3e, n4, n7, 28nm) with significant exposure to TSMC and Samsung foundries. - Focus on ppa & time to market driven sign-off strategy based on products like mobile, auto or comput as well as segment of product (like elite to entey leave) TECHNICAL SKILLS: ● ASIC - Physical Design Netlist to GDSII flow. ● Hands on experience in Floorplaning. Placement, CTS, Route. ● Hands on experience in debugging timing critical block. ● Strong on synthesis & Static Time Analysis. ● strong on Timing signoff strategy & constraint writing for CPU. ● Scripting Languages: TCL, Shell Tools Known: Logic Synthesis: Cadence RTL Compiler, Synopsys DC compiler Place & Route: Cadence Encounter. Signoff Tool: Cadence Tempus, Prime Time (STA). Timing Fixing in Tweaker / PT DMSA

Stackforce AI infers this person is a VLSI design expert with a focus on mobile and automotive chip development.

Location: Bengaluru, Karnataka, India

Experience: 12 yrs 1 mo