R

Rahul Sharma

Director of Engineering

Hyderabad, Telangana, India26 yrs 7 mos experience

Key Highlights

  • 26+ years in ASIC design and verification.
  • Expertise in SOC design from specifications to delivery.
  • Proficient in multiple hardware description languages.
Stackforce AI infers this person is a seasoned ASIC design engineer with extensive experience in hardware design and verification.

Contact

Skills

Core Skills

Soc DesignProject Engineering

Other Skills

VerilogVHDLC/C++VeraSpecmanSynopsys Design CompilerPrimetimeVerilog-AMSLow-power DesignProcessorsHDMI

About

Have been working for 26+ years in ASIC design/verification for networking, Video, Graphics, Display and Processors. I have worked on DSPs and PCI and other bus protocols. I have also worked on high speed serial buses like Serial-ATA and PCI Express. Specialties: Verilog, VHDL, C/C++, Vera, Specman, Synopsys Design Compiler, Primetime, Verilog-AMS for mixed signal simulations.

Experience

26 yrs 7 mos
Total Experience
2 yrs 1 mo
Average Tenure
4 mos
Current Experience

Azimuth ai

Director SOC Design

Jan 2026Present · 4 mos · Hyderabad, Telangana, India · On-site

  • Heading the SOC design team to get the SOC designed from specifications to the final chip being delivered to customer.
SOC designProject Engineering

Drut technologies inc

Director of Engineering

Apr 2024Feb 2025 · 10 mos · Hyderabad, Telangana, India · On-site

Project Engineering

Amd

SMTS Silicon Design Engineer

Mar 2023Apr 2024 · 1 yr 1 mo · Hyderabad, Telangana, India · On-site

Project Engineering

Excelmax technologies

Director Of Engineering

Sep 2019Mar 2023 · 3 yrs 6 mos · Bangalore, India · On-site

Project Engineering

Spectoss inc

Consultant

Feb 2019Sep 2019 · 7 mos · Greater Delhi Area

  • Spectross has developed reconfigurable compute machine known as HPRCM which has 78 no. FPGAs and 14 no. Power PC Processor. It also an Application Development Framework for porting of applications. I have two main responsibilities :
  • Porting of customer applications to HPRCM in the area of Cryptology and Bio-Informatics
  • Defining & architecting the next generation HPRCM and its implementation
  • My team consists of RTL Designers, Embedded Hardware Designers and Embedded Software Designers.
Project Engineering

Jorzu design inc

Vice President Of Engineering

Jun 2009Feb 2019 · 9 yrs 8 mos · Sunnyvale, CA, USA

  • Provided foresight into innovations in products, built budgets for products according to inputs from marketing. Managed a large team of engineers over different functional groups of engineering to get products designed in time and within budget while keeping quality at getting a good working silicon at first fabrication.
  • Working on architecture design for Video Transcoder for medical device applications. Working on writing design documents, system C coding for transcoder algorithms.
Project Engineering

Silicon image inc

Sr. Manager

Mar 2003Jun 2009 · 6 yrs 3 mos · Sunnyvale, CA, USA

  • Managed large and small teams to complete projects on time and within budget.
  • Worked on DVI, HDMI, PCI-Express, SATA and Graphics Scalar chips and IP Cores in field of design, verification, synthesis, STA and working with Test Team.
Project Engineering

Sun microsystems

2 roles

Manager

Promoted

Sep 2002Mar 2003 · 6 mos · Newark, CA, USA

  • Managed a team of 10 engineers to design and verify asics and FPGAs.
  • Worked on Verification of ASICs using vera and other industry standard tools. Well versed with Sun's verification methodology.
Project Engineering

MTS-Hardware

Jan 2001Dec 2001 · 11 mos

  • Worked as ASIC Verification consultant using Vera for verification. Other industry standard tools were also used.
  • Helped in Synthesis as well.

Propulsion networks

Member Technical Staff

Dec 2001Sep 2002 · 9 mos

  • Worked in verification of Networking ASIC using Vera and other industry standard tools.
Project Engineering

Infineon technologies

Verification/Design Consultant

Sep 2000Jan 2001 · 4 mos

  • Worked as Consultant, was responsible for fullchip synthesis, static timing analysis, verification and RTL modifications.

Cmos chips

Member Technical Staff ( Consulting )

Jan 2000Jan 2001 · 1 yr

Philips semiconductors

Verification/Design Consultant

Dec 1999Sep 2000 · 9 mos

  • Worked at Philips Semiconductors in verification, synthesis and RTL coding using specman, verilog, C/C++ and other tools.

Duet technologies

AMTS

Jan 1998Jan 1999 · 1 yr

Education

San José State University

MS — Engineering

Jan 2003Jan 2005

Thapar Institute of Engineering & Technology

BE-EC — Electronics Communication

Jan 1994Jan 1997

Delhi Public School - R. K. Puram

Jan 1990Jan 1993

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