Apr 2019 – Sep 2020 · 1 yr 5 mos · Bengaluru Area, India

• 12 bit ADC, 5GHz VCO, 10GHz VCO, phase detector, frac-N PLL loop/phase noise modelling and lab correlation, TX architecture, Two point modulation for GFSK, 8-bit DAC, sigma delta dividers, external cap LDOs, bandgap etc

Nov 2017 – Mar 2019 · 1 yr 4 mos · Bengaluru Area, India

• 13GHz LC oscillator for accurate Tpdm callibration, evaluation of temperature drift of inductors due to various loss mechanisms and skin effect, clocking architecture proposal/evaluation for minimizing Tdynoff, 2.4GHz Clock receiver for minimum VT drift, 2.4GHz DFE based data receiver, 7 bit phase interpolator for 800MHz clock, low VT drift fixed delay generation, DLL period jitter modelling, DCD callibration, RC oscillator, Tqsk adjust cell, Tqsk mechanism, VT drift evaluation for various blocks, 2.4GHz ring oscillator, bandgap, voltage regulators, offset cancellation through chopping, 13GHz TSPC based dividers, etc.
• Helping new joinees with their ramp up

Jun 2016 – Sep 2017 · 1 yr 3 mos · Bengaluru Area, India

• 56Gbps PAM-4 Transmitter on 16nm finfet, SST drivers, equalization, half rate serializer, matlab modelling of clock jitter's impact on the eye margins, bandwidth extension techniques (series peaking, tline, T-coil), crosstalk impact on jitter etc. Familier with Serdes TX architecture tradeoffs.
• Clock distribution, DCD callibration, 14GHz LC VCO, VCO pulling, Bandgap/bias generation block.
• Good understanding of the quality factor impairments for inductors.
• Familiarity with phase interpolaters, crystal oscillators etc.

May 2015 – May 2016 · 1 yr · Bengaluru Area, India

• Tx Baseband filter design -- various topologies for bilinear and biquad filters. Class A/AB topologies. 4FMOD/power/RxBN tradeoffs. Preemphasis for RxBN improvement vs group delay tradeoff. Twin-T notch filters for better DAC image rejection.
• Harmonic rejection techniques for HD3 improvement/low-band inductor elimination.
• IM3 cancellation techniques for improving pre-driver distortion.
• Twin-T attenuators for better carrier suppression.
• Correlation with lab measurements etc
• Previous project pitfalls-> specifically design flaws arising out of designer's "bias" towards patentable ideas.
• Mentoring juniors

Jul 2012 – Apr 2015 · 2 yrs 9 mos · Bengaluru Area, India

• Designed a 10-bit, 8 channel SAR ADC with less than 1LSB INL and DNL in a 28nm TSMC process
• Digital PLLs,
• Signal chain for a 4-20mA interface, 200V class-AB driver for piezoactuator applications using 100V transistors in an ABCD process,
• 100V to 200V charge pump,
• voltage regulators, bandgaps,
• 100MHz PCIe clock slicers,