Lava Kumar

Director of Engineering

Bengaluru, Karnataka, India19 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Leader of a 52-engineer team in SRAM design.
  • 12 US patents in circuit design innovations.
  • Expert in delivering high-performance memory IP.
Stackforce AI infers this person is a Semiconductor Engineering Leader with expertise in SRAM and memory compiler development.

Contact

Skills

Core Skills

Team LeadershipSram DesignCircuit DesignProject ManagementMemory Design

Other Skills

Cross-functional Team LeadershipCritical ThinkingAnalytic Problem SolvingCollaborative Problem SolvingProject PlanningSi debugASICIntegrated Circuit DesignSemiconductorsDigital ElectronicsStatic Timing AnalysisPhysical DesignVLSISoCTiming Closure

About

As the leader of a talented team of 52 engineers specialized in SRAM circuit design, I focus on developing SRAM, RF, and ROM memory compilers tailored to the most advanced technology nodes. My role centers on delivering high-performance, high-density, and low-power SRAM IP that enables cutting-edge SoCs across the segments like AI, Hyper scalars, Application Processors, Automotive etc. With two decades of experience in the field of circuit design, I thrive on solving complex challenges through innovative techniques. This belief has led to 12 US patents and fruitful collaborations with global teams in Korea and the US, reflecting a commitment to pushing the boundaries. Achieving tough PPA targes with aggressive schedule has always excited me. I’m driven by a passion for solving complex problems in silicon design and a belief that the best solutions come from a blend of expertise, creativity, and teamwork. Continuously refining process and technology to exceed expectations energizes me. Specialties: * Good understanding of Circuit Design fundamentals * Hands on experience in the Circuit Design * Rich experience in leading a team while giving technical guidance to the team. *Understanding customer requirements and delivering quality IP on time. *Project planning and execution at aggressive timelines *Building and Leading High performance teams

Experience

19 yrs 8 mos
Total Experience
4 yrs 11 mos
Average Tenure
11 yrs 8 mos
Current Experience

Samsung semiconductor

4 roles

Director

Promoted

Mar 2026Present · 3 mos

  • Leading a team of 52 talented engineers for the past two years. Delivering high performance, high density and low power SRAM IP for the Samsung Foundry customers.
Cross-functional Team LeadershipTeam LeadershipSRAM Design

Associate Technical Director

Mar 2020Mar 2026 · 6 yrs

  • Leading a team of 52 highly talented engineers in the field of SRAM circuit design. Developing SRAM, RF, ROM memory compilers, across the most advanced technology nodes to cater to the needs of Samsung Foundry customers.
Circuit DesignCritical ThinkingAnalytic Problem SolvingCollaborative Problem SolvingProject PlanningSi debug+1

Senior Chief Engineer

Promoted

Mar 2017Feb 2020 · 2 yrs 11 mos

  • Lead a Team of engineers to develop on-chip memories (SRAM, 2-Port RF and VROM) in Fin-Fet based cutting edge technology.
Critical ThinkingMemory Design

Chief Engineer

Aug 2014Feb 2017 · 2 yrs 6 mos

  • Joined a fresh team at SAMSUNG Bangalore. Built Single Port Memory Compiler Development in 28nm Technology from scratch. Developed robust methodology and verified the design from all angles. Tasted success in the first silicon.

Texas instruments

2 roles

Lead Engineer

Jun 2012Jul 2014 · 2 yrs 1 mo · Bengaluru Area, India

  • Promoted to Lead Engineer for memory compiler development.

Senior Memory Design Engineer

Jan 2011Jun 2012 · 1 yr 5 mos · Bengaluru Area, India

  • Played key role in developing 45nm High speed memory compiler development.

Amd

Design Engineer II

Jul 2007Jan 2011 · 3 yrs 6 mos

  • Worked on Register Files, ROMs, RAMs, Digital Frequency Synthesizer and various Custom Digital Circuits.
  • Performed Voltage Domain Crossing, Clock Domain Crossing analysis at Chip level.

Lsi technologies india bagalore

Design Engineer

Jul 2006Jul 2007 · 1 yr

  • Worked on memory compiler design methodology.

Education

Indian Institute of Technology, Kanpur

M.Tech — Microelectronics & VLSI Design

Jan 2004Jan 2006

Sree Vidyanikethan Engg College

B Tech — Electronic and Communications

Jan 1999Jan 2003

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