Rishabh Gupta — Software Engineer
Technical Skills: Well versed with ASIC flow (RTL to GDSII) and the stages involved in physical design flow (APR). Understanding of good Floorplan methodology with data flow diagram of high macro count. Efficient in timing aware, congestion driven macro placement during Floor-planning, Power planning with IR drop and EM analysis. Sound Knowledge of STA: OCV, Timing analysis of latch, CRPR, Effects of clock skew on timing, Fixing timing violations. Knowledge of Synthesis. Interpretting Timing Reports. Proficient in scripting language PERL and TCL. Experienced with Linux/Unix. Knowledge of CMOS device. Knowledge of Verilog HDL.
Stackforce AI infers this person is a Digital ASIC Design Engineer with expertise in Physical Design and Static Timing Analysis.
Location: Bengaluru, Karnataka, India
Experience: 8 yrs 11 mos
Skills
- Physical Design
- Digital Asic Design
Career Highlights
- Expert in ASIC design from RTL to GDSII.
- Proficient in timing analysis and fixing violations.
- Skilled in scripting with PERL and TCL.
Work Experience
Texas Instruments
Senior Design Engineer (4 yrs 4 mos)
STMicroelectronics
Senior Design Engineer (2 yrs 10 mos)
Intel Corporation
Physical Design Engineer (1 yr 2 mos)
RV-VLSI VLSI and Embedded Systems Design Center
Trainee (7 mos)
Education
Post Graduate Diploma at RV VLSI DESIGN CENTER
Bachelor of Engineering (B.E.) at Acropolis Group of Institutions
Primary Education at Mahatma Gandhi Convent H.S. School, Shajapur(M.P.)
