Abhishek Shende — Intern

I am a VLSI RTL, DFT and Physical Design Engineer. I have completed my course from Maven Silicon Bangalore in VLSI RTL Design and DFT. - DFT Tessent Tool (Mentor Graphics) (RISC V DFT: Scan Chain | ATPG | EDT IP | Improve test coverage) I have also completed my course from ChipEdge Technologies, Bangalore, in VLSI Physical Design(Synopsys) and another course of Cadence commands (INNOVUS) from VLSI Guru. Skills :- - Digital Circuits - CMOS - Verilog (Router Protocol & RISC V) Technology Node 28 nm and 14 nm - Synthesis using DC Compiler (logical and physical aware). - Data Preparation, Floorplan, Powerplan, Placement, Clock Tree Synthesis, Routing (IC Compiler 2), - RC extraction using Star RC - Static Timing Analysis using Prime Time. - Physical Verification using IC validator - Cadence (Innovus) commands from VLSI Guru Projects :- ORCA, JBI, Falcon, DTMF ChipTop and Router 1x3

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and DFT methodologies.

Location: Nagpur, Maharashtra, India

Experience: 1 yr 2 mos