Siddhartha Gupta

Software Engineer

Bengaluru, Karnataka, India1 yr 9 mos experience

Most Likely To Switch

Key Highlights

Expert in SOC and IP verification methodologies.
Strong background in cryptography and security protocols.
Proven track record in debugging complex semiconductor designs.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in SOC and cryptographic systems.

Contact

siddhartha.gupta119@gmail.com LinkedIn

Skills

Core Skills

Soc/subsystem/ip VerificationUvmTrngDebuggingCryptographyIp VerificationFunctional Verification

Other Skills

CPUJTAG/IJTAGSystem VerilogBus Protocols- AXIUARTQRNGSRAMCryptoAXIVerificationDDR SDRAMSynopsys VCSVerdiCadence VirtusoDFT

About

Professional Knowledge CPU Subsystem | JTAG/IJTAG | System Verilog | UVM | SOC/Subsystem/IP Verification | Bus Protocols- AXI, APB, AHB | Communication Protocols- UART, GPIO, TRNG Passion is what makes you keep motivated and lively. Back in childhood, I enjoyed playing piano, but I was also keen, how inside electronics worked making beautiful sounds. This curiosity of mine led me to do BTech followed by MTech in Microelectronics. The fact that millions of transistors are what makes our life easier is what excites me always. I am glad to choose a career as a design and verification engineer which will help me quench the thirst of my curiosity. Connections are welcome from those who want to discuss hardware design, verilog, system verilog, UVM, Music and Marvel Movies ✌🏻🙂

Experience

1 yr 9 mos

Total Experience

10 mos

Average Tenure

1 yr 5 mos

Current Experience

Quest global

Senior DV Engineer

Jan 2025 – Present · 1 yr 5 mos · Bengaluru, Karnataka, India · Hybrid

Currently working with DFX-DV Server team in AMD.
Worked on in-house CPU subsystem consisting of ARM Cortex-A55.
Performed CPU bring-up verification by executing C-based sanity loops for a heartbeat toggling pattern
Designed and executed a UART-based CPU bring-up test using C to verify
CPU reset, instruction execution, and peripheral connectivity by printing
boot messages over memory-mapped UART
Developed a C-based RAM access test to verify data integrity by writing
known patterns and validating expected values in memory bank
Developed a GIC-to-CCI integration test using UVM by driving AXI
transactions through the Cache Coherent Interconnect to program and
read GIC registers
Worked in close collaboration with Quest’s Vietnam verification team to
align test strategies, debug issues, and achieve coverage goal

CPUJTAG/IJTAGSystem VerilogUVMSOC/Subsystem/IP VerificationBus Protocols- AXI+1

Digicomm semiconductor

Senior Engineer-DV

Sep 2024 – Jan 2025 · 4 mos · India · On-site

Worked with Qualcomm's PRNG, TRNG and QRNG consisted of SRAM bit-cell for entropy source.
Worked on bug for overflow handling of random bits. Caused bits generation beyond upper limit range without wrapping around
Worked on TRNG using RO.
Identified bug in QRNG entropy output (repetitive 1) caused by lack of frequency detuning in RO
Developed interrupt and negative testcases for TRNG for intermittent and permanent failure
Reported design bug for NIST incompliance, interrupt not flagged in RCT due to missing address mapping for failure cases.
Involved in QRNG block utilizing bit-cells for true random number generation.
Regression bucket analysis and debugging for PRNG & TRNG majorly

TRNGQRNGSRAMDebugging

Qualcomm

Engineer II - Verification

Jan 2024 – Oct 2024 · 9 mos · Bengaluru, Karnataka, India · On-site

Got an opportunity to work with QC's Security Team where I handled Crypto Engine in SOC and IP mode.
Have knowledge on different cryptographic and authentication operations such as ECB, CBC, SHA, • • Hashing, CTR, GCM, CCM, SM3, SM4. This ensure tight security around data transfers without worrying much about hacks.
Verified cryptographic engine at SoC level for automotive grade use case
Developing sequences and implementing checkers, targeting a low
power crypto processor integrated with wireless display subsystem
Tested AXI timeout behavior by power down of module and checking
stalled ready/valid handshakes during PA verification.
Developed checkers to check isolation enable before power down
Fired regressions

CryptoCryptographyAXIVerificationIP Verification

Microchip technology inc.

Consultant-Design Verification Engineer

Mar 2022 – Dec 2023 · 1 yr 9 mos · Bengaluru, Karnataka, India

Worked with DCS (Data Center System) team on their Flashtec® NVMe® Controller which will be used for controlling SSD in large enterprises/data centers.
Was on a contract role from Krisemi Design Technology.
Responsibilities:-
>Working on both IP and SOC level on multiple blocks.
>Creating test plans.
>Running regressions & debugging test cases and checking for RTL bugs.
>Blocks Worked=>
Accelerator Subsystem [SOC]
Data Processing System [SOC]
PVT (Process Voltage Temperature) [SOC]
Peripherals (GPIO, SPI, UART, SMBus, SSMBus, TRNG) [SOC/IP]

IP VerificationDebuggingFunctional VerificationDDR SDRAM

Maven silicon

Design and Verification Trainee

Jul 2019 – Apr 2020 · 9 mos · Bengaluru, Karnataka, India · On-site

Aditya birla chemicals

Internship

Dec 2017 – Jan 2018 · 1 mo · Jagdishpur Industrial Area, Distt: Amethi

After my 5th semester, I used my semester break for doing 4 weeks internship in Instrumentation Department. During my Internship I worked on Control System and Other Devices.