Deepak Kumar

Product Engineer

Bengaluru, Karnataka, India4 yrs 10 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Specialized in RTL-to-GDSII flow using Synopsys Fusion Compiler.
Experience across multiple technology nodes from 1.4nm to 350nm.
Proficient in scripting languages including Python and Tcl.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in FPGA and VLSI technologies.

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Skills

Core Skills

Field-programmable Gate Arrays (fpga)Vhdl

Other Skills

FcICCTCLMATLABXilinx VivadoPhysical DesignRTL to GDSIISynopsys Fusion CompilerPlace & Route (PnR)Static Timing Analysis (STA)Static Timing AnalysisClock tree synthesisFloor-planningSynthesisPerl

About

✤ Results-driven Senior Physical Design Engineer with 3+ years of experience specializing in advanced semiconductor design. ✤ Expertise in RTL-to-GDSII flow using Synopsys Fusion Compiler, including synthesis, floor-planning, power planning, clock tree synthesis (CTS), and place and route (PnR). ✤ Experience across multiple technology nodes including 1.4nm, 2nm, 16nm, and 350nm. ✤ Proficient in scripting languages such as Python, Perl and Tcl.

Experience

4 yrs 10 mos

Total Experience

2 yrs 5 mos

Average Tenure

3 yrs 11 mos

Current Experience

Synopsys inc

2 roles

R&D Engineering, Sr Engineer

Promoted

Feb 2025 – Present · 1 yr 4 mos · Bengaluru, Karnataka, India

R&D Engineering Engineer

Jul 2022 – Feb 2025 · 2 yrs 7 mos · Bengaluru, Karnataka, India

FcICC

Coreel technologies

FPGA Design Engineer

Aug 2021 – Jul 2022 · 11 mos · Bengaluru, Karnataka, India

➤Worked on transmitter part of Radar and generated the Single-Tone and chirp signal for DAC.
➤Worked on Programming Languages like VHDL, MATLAB, TCL.
➤Knowledge on tools like Xilinx Vivado, MATLAB, Octave, TICS Pro, DAC39J82EVM,
Microsoft Visio, Tortoise SVN.
➤Worked on RTL integration, synthesis, static timing analysis(STA) and clock domain crossing(CDC)
➤On-chip debugging of FPGA designs using Vivado hardware debug tool.
➤Experience in Board bring up and validation with test RTL and TCL script.
➤ Worked with signal analysis instruments like Storage Oscilloscopes and Spectrum Analyzers.
➤Experience in usage of interfaces like JTAG, UART, DDR4, QSPI, IIC, JESD204B, DAC SPI, LMK SPI.

VHDLField-Programmable Gate Arrays (FPGA)