Phalguni Bala

CEO

Bengaluru, Karnataka, India23 yrs 9 mos experience

Highly Stable

Key Highlights

24 years in high-speed electrical interface design
Expertise in memory interface designs including GDDR and HBM
Strong leadership in cross-functional team development

Stackforce AI infers this person is a seasoned expert in high-speed memory interface design within the semiconductor industry.

Contact

Skills

Core Skills

Memory Interface DesignMemory Phy DevelopmentAnalog & Mixed Signal Design

Other Skills

HBM memory interface developmentGDDR memory interface developmentArchitecture designMicro-architecture developmentCustomer supportArchitecture developmentAMS designLogic designHSLink Analog Front End DesignHSLink Analog Back End DesignAnalog Mixed Signal DesignAnalog Circuit DesignSpice SimulatorHigh speed link transceiver designKnowledge about digital design flow

About

Working in the high speed electrical interface design for about 24 years. - Strong cross-functional leadership, customer engagement and team development experience - Expertise in the memory interface designs, GDDR6/7, HBM2E/3. DDR3/4 - Architected and led a number of memory PHY development from spec to silicon as cross-functional lead(CTL) - Led development a number of HBMI Tx/Rx interface PHYs as PHY and AMS lead - Hands on experience in layout, RTL coding, STA - Excellent understanding on system design issues. - Excellent understanding of package substrate, interposer, PCB designs challenges.

Experience

23 yrs 9 mos

Total Experience

9 yrs 6 mos

Average Tenure

4 yrs 8 mos

Current Experience

Cadence

2 roles

Design Engineering Group Director

Promoted

Jul 2025 – Present · 11 mos

Leading HBM and GDDR memory interface development.

HBM memory interface developmentGDDR memory interface developmentMemory Interface Design

Design Engineering Director

Oct 2021 – Jul 2025 · 3 yrs 9 mos

Led architecture, micro-architectures and development of successful GDDR7 and HBM4 memory PHYs. supporting customers to develop their SOCs with these PHYs.

Architecture designMicro-architecture developmentCustomer supportMemory PHY Development

Rambus

Sr. Manager, Circuit Design Engineering, Memory Interfaces

Jul 2015 – Sep 2021 · 6 yrs 2 mos

Developed architecture and worked on AMS design of HBM3, HBM2/E, GDDR6, DDR3/4 PHYs

Architecture developmentAMS designMemory Interface Design

Synopsys inc

Analog & Mixed Signal Engineer

Apr 2015 – Jun 2015 · 2 mos · Noida Area, India

St microelectronics

Analog & Mixed Signal Engineer

Apr 2002 – Mar 2015 · 12 yrs 11 mos · Noida, Uttar Pradesh, India

Worked on AMS and logic design of HDMI interface and USB2. Also worked on analog IPs like LDOs, voltage reference, ADC, oscillator and charge pump circuits.

AMS designLogic designAnalog & Mixed Signal Design