Vikas Kumar — Software Engineer

Objective: To be a part of vlsi design and verification industry. Experience in writing RTL models in Verilog HDL and Testbenches in SystemVerilog.Very good knowledge in verification methodologies. Experience in using industry standard EDA tools for the front-end design and verification. Interested in working in semiconductor industry. Specialties: HDLs: Verilog HVL: SystemVerilog, UVM EDA Tool: VCS, NCSIM, Specman, Modelsim, Xilinx-ISE Domain: ASIC/FPGA Design Flow, Digital Design methodologies Knowledge: RTL Coding, FSM based design, Simulation, Code Coverage, Functional Coverage, Synthesis

Stackforce AI infers this person is a VLSI design and verification expert with extensive experience in semiconductor industry.

Location: Noida, Uttar Pradesh, India

Experience: 15 yrs 7 mos