S

Sukrutha Gundappa

Product Manager

Bengaluru, Karnataka, India14 yrs 9 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 14+ years in Semiconductor Industry
  • Expert in Foundation IP and Standard Cells
  • Proven track record in innovative semiconductor solutions
Stackforce AI infers this person is a Semiconductor Industry Expert with a focus on R&D and design methodologies.

Contact

LinkedIn

Skills

Core Skills

Foundation IpStandard Cells

Other Skills

Logic Libraries characterizationStandard cells developmentLayout DesignFull/Semi Custom cells design and characterizationASIC layout designStandard cells LayoutProject ManagementLogic library development

About

With over 14+ years of experience in Semiconductor Industry, currently serving as R&D Manager @Synopsys Inc., I specialize in Foundation IP - standard cells, full/semi custom cell design, layout and characterization. My collaborative approach empowers teams to develop innovative, high-performance semiconductor solutions that align with Synopsys's mission of driving technology forward. Focused on delivering impactful results, I bring a commitment to excellence, fostering innovation, and creating value through efficient and scalable design methodologies.

Experience

14 yrs 9 mos
Total Experience
3 yrs 8 mos
Average Tenure
6 yrs 4 mos
Current Experience

Synopsys inc

3 roles

R&D Manager

Promoted

Jan 2024 – Present · 2 yrs 5 mos

Logic Libraries characterizationStandard cells developmentFoundation IPStandard Cells

R&D Engineer Sr II

Jan 2022 – Jan 2024 · 2 yrs

Layout Design

A & MS Engineer Sr 1

Feb 2020 – Jan 2022 · 1 yr 11 mos

Invecas

Member Of Technical Staff

Sep 2016 – Feb 2020 · 3 yrs 5 mos · Bengaluru, Karnataka, India · On-site

  • Standard cells Layout and Characterization
  • Custom Layout design
Logic Libraries characterization

Synopsys inc

A&MS Layout Design Engineer

Jul 2012 – Aug 2016 · 4 yrs 1 mo · Bangalore

Tata elxsi

Layout Design Engineer

Jul 2011 – Jun 2012 · 11 mos · Greater Bengaluru Area

  • Memory and Standard cell layout design

Education

Visvesvaraya Technological University

Electrical and Electronics Engineering

Aug 2007 – Jun 2011

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