Akash Acharya

Product Manager

Bengaluru, Karnataka, India6 yrs 11 mos experience
Most Likely To SwitchAI Enabled

Key Highlights

  • Expertise in VLSI with hands-on experience in leading-edge technology.
  • Significant contributions to multiple tapeouts in advanced CPU designs.
  • Proficient in leveraging ML tools for optimization in physical design.
Stackforce AI infers this person is a VLSI Design Engineer specializing in advanced semiconductor technologies.

Contact

Skills

Core Skills

Cadence Cerebrus

Other Skills

Cerebrus AI StudioArea shrinkCadence JedAITiming ClosureTcl/shellInnovusPandas (Software)Power OptimizationCadence Cerebrus MLSTAUniversal Verification Methodology (UVM)UnixShell ScriptingC++Microsoft Office

About

Very passionate about VLSI and want to progress in the field to be the best. -> I have worked in Intel core team on memory cluster and out of order cluster part of the 5nm cpu core project. -> I have worked on synthesis to signoff flow for Samsung 4nm,5nm technology projects -> I have experience working with Cadence machine learning cerebrus tool to achieve better PPA on 4nm and 5nm cpu designs. -> Cadence Korea onsite Support for top design 3DIC based testchip for samsung foundry project -> I have worked on the 3GAP based testchip tapeout as a part of the PnR innovus implementation team and have worked on timing closure and DRC closure on multiple blocks. -> I have been part of four tapeouts in which I have owned multiple blocks and I have run the implementation part of the flow. -> I have good exposure to the latest ML/AI tools like Cadence Cerebrus ML and Cerebrus AI Studio.

Experience

6 yrs 11 mos
Total Experience
3 yrs 5 mos
Average Tenure
6 yrs 4 mos
Current Experience

Cadence design systems

3 roles

Principal Product Engineer

Promoted

Jul 2024Present · 1 yr 11 mos

Cadence CerebrusCerebrus AI Studio

Lead Product Engineer

Promoted

Jun 2022Jul 2024 · 2 yrs 1 mo

Cadence Cerebrus

Product Engineer 2

Feb 2020Jun 2022 · 2 yrs 4 mos

Cadence Cerebrus

Singularity dynamics pvt ltd

Chip Verification Engineer

Jun 2019Jan 2020 · 7 mos · Bangalore

  • Pipelined debugging and understanding of modern computer core architecture using formal verification tool

Intel corporation

Digital Design Intern

Jul 2018Jun 2019 · 11 mos · Bengaluru, Karnataka, India

  • Digital design intern , Intel Big Core(C2DG) Team

Education

School of Information Science, Manipal

Master of Engineering — VLSI DESIGN

CMR Institute Of Technology

Bachelor of Engineering (BE) — electronics and communication engineering

Jan 2011Jan 2015

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