Jun 2023 – Oct 2024 · 1 yr 4 mos · Austin, Texas, United States · On-site

Feb 2021 – Jun 2023 · 2 yrs 4 mos

• Program manage a large portfolio of SoC-server IPs across multiple SoC programs and generations, ensuring on-time SoC delivery, issue mitigation or escalation, change-control board (CCB) ownership, and external status communications.
• Manage the definition and implementation of modern metrics, indicators, and dashboards for adoption across the entire Program Management Office portfolio and ecosystem, working to EOL old and ineffective legacy indicators

Apr 2017 – Jan 2021 · 3 yrs 9 mos

• Manage a global team of software engineers and data scientists tasked with increasing data center performance (i.e. servers, CPUs, memory & storage) through SaaS and IaaS solutions.
• Program Managed the largest software-tool EOL in Intel history, removing over 2400 obsolete or vulnerable tools without impacting a single customer.
• Collaborated with external organizations to identify AI/ML enhancement opportunities, architecting new solutions utilizing cutting-edge machine learning techniques. Program managed the development and deployment of SaaS/IaaS solutions across Intel’s cloud computing data centers throughout the world.
• Program managed the development and deployment of funded initiatives across multiple, globally deployed teams, who in two years delivered over 10 years of time-to-market acceleration to our customers across Intel. The program delivered over $73M in capital-expenditure savings in 2019 and $100M in 2020.
• Report quarterly key performance indicators (KPI) to the CIO and their staff of senior VPs, outlining initiative progress and quarterly capitol savings.
• Led the global effort to transition a large department into Scaled-Agile Framework (SAFe) structured around a single value-stream yielding 12 scrums; took on the role of Release-Train Engineer (RTE), developed and conducted all training and coordinated all program-increment planning activities.

Oct 2015 – Apr 2017 · 1 yr 6 mos

• Managed the USB IP pre-Si validation organization, the largest and most prolific IP in Intel. The team spanned Folsom, Penang, Bangalore, and Beijing with over 35 full-time and contract engineers, including 2 managers under my leadership.
• Developed and implemented yearly budgets to meet staffing and development goals.
• Presented quarterly status updates and KPIs to the Chief Engineering Officer and his staff, up leveling the data for senior management consumption.
• Program managed the pre-Si design and validation activities for all USB deliveries to customer SoCs, delivering multiple divergent versions at the same time, and was directly accountable for the silicon quality of each.
• Implemented Agile-Scrum methodology to plan and track deliverables and operated as the Product Owner for validation-collateral scrums, and Scrum Master for an inter-discipline feature-delivery scrum consisting of architecture, design, and validation engineers.

Jan 2013 – Oct 2015 · 2 yrs 9 mos

• Responsible for the management and career development of a team of engineers focused on two separate areas, mixed-signal validation and functional validation.
• Project managed all validation activities and methods of 6 IPs across two programs, including environment development, OVM testbenches, architecture and design validation, constrained-random testing, functional-coverage development and collection, setting team objectives, adjusting priorities and assignments, tracking progress and ultimately meeting all defined milestones.
• Owned full-chip SoC clock validation, including dynamic-clock gating, boot PLL and power-control unit interaction, clock spines and all PLL partition interactions to name a few.
• Responsible for coordinating all hiring and on-boarding activities for the Architecture-Validation team. Directly responsible for coordinating the recruitment and hiring of engineers. Instituted processes for training and integrating new hires and established numerous teambuilding and recognition practices to enhance work-place morale & effectiveness.

Jan 2012 – Dec 2012 · 11 mos

• Designed enhancements for a DisplayPort PHY, which encompassed changes to every major area of the IP.
• Architected and designed digital offset-cancellation algorithms for new analog circuitry.
• Re-architected large portions of multiple PHYs to remove obsolete logic, improving flop counts and reducing area.

Jun 2011 – Dec 2011 · 6 mos

• Led a team of engineers to validate all mixed-signal IPs on a mobile SoC, including several new MIPI based PHYs.
• Validated all full-chip mixed-signal interactions, including PLLs and clocking networks.
• Integrated multiple IPs into the full-chip SoC model.

May 2009 – Jun 2011 · 2 yrs 1 mo

• Created custom SystemVerilog testbenches to carry out analog mixed-signal validation (MSV/AMS) on many IPs, including PCIe Gen3 PHY, DisplayPort PHY, MIPI DSI and MIPI CSI across client and mobile projects.
• Created and executed IP testplans for digital and analog functionality, with an emphasis on analog and digital interactions.
• Developed SystemVerilog assertions for serial IOs, validating data path integrity, compensation mechanisms and offset-cancellation algorithms to name a few areas.

Jun 2008 – Apr 2009 · 10 mos · Rochester, Minnesota

• Architected a standardized LBIST solution connecting to the scan chains and authored the testplan.
• Scan stitched netlists with multiple ATPG tools, debugged incorrect scan chain configurations and resolved low coverage numbers.
• Developed a methodology to create flattened gate-level synthesized netlists from hierarchical RTL models using Synopsys Design Compiler, allowing the ATPG group to work on netlists months before their scheduled release.

Mar 2005 – Jun 2008 · 3 yrs 3 mos · Austin, Texas

• Designed reusable MISR, PRPG, and LFSR RTL modules for use across multiple projects, and developed C++ reference models to verify BIST algorithms on arrays and ROMs.
• Verified JTAG and BSDL with custom SystemVerilog testbenches, both at the IP and gate-level full-chip models; generated JTAG ATPG patterns for production testing and fault-grading analysis, which was an AMD first winning me a spotlight award.
• Verified a HIP JTAG controller using off-the-shelf tools by creating BSDL with no BSR definition, and submitted a paper outlining this new approach to the International Test Conference.
• Performed ATPG library-cell processing and verification of a TSMC standard-cell library, a full-custom low-power Mux-D library and custom LSSD cells; carried out test insertion and scan stitching on synthesized netlists, monitoring various methods of scan-chain balancing.

May 1998 – Jan 2003 · 4 yrs 8 mos · Austin, Texas

• • Performed device characterization, data analysis, and yield tracking of microprocessor engineering samples with ATE.