ANUP KUMAR

Software Engineer

Bengaluru, Karnataka, India4 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

4 years of experience in Mixed Signal Logic Design.
Expertise in UCIe and SerDes protocols.
Strong background in VLSI Design and RTL development.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Mixed Signal Logic and VLSI technologies.

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Skills

Core Skills

Rtl DesignSerdesUcie

Other Skills

Universal Chiplet Interconnect Express (UCIe)Multi-Gigabit Serializer/Deserializer (SerDes)Deskew & DCC CalibrationsFIFOClock Domain Crossing (CDC)Power SimulationStatic Timing AnalysisCMOSLPDDR PHY Designm-PHY DesignUFS 5.0Semiconductor Technology and Integrated CircuitsSpyGlass Lint & CDCKnowledge of Digital logic and optimizationKnowledge of VLSI Design/RTL Coding/FPGA

About

4 years of experience as an Mixed Signal Logic Design Engineer, working on cutting-edge IP/SoC architectures, advanced Silicon design and process technologies. Education : • MTech in Microelectronics and VLSI Design from the Indian Institute of Science Bangalore (IISc) • BTech in Electronics and Communication Engineering from Guru Gobind Singh Indraprastha University (GGSIPU), New Delhi Technical Skills: • Universal Chiplet Interconnect Express (UCIe) Protocol for Advanced Package • Multi-Gigabit Serializer/Deserializer (SerDes) • LPDDR PHY Design • m-PHY Design • UFS 5.0 • Semiconductor Technology and Integrated Circuits • SpyGlass Lint & CDC • Knowledge of Digital logic and optimization • Knowledge of VLSI Design/RTL Coding/FPGA • Knowledge of RTL tools/flows • Good problem solving and analytical skill

Experience

4 yrs 3 mos

Total Experience

2 yrs 1 mo

Average Tenure

3 yrs 11 mos

Current Experience

Intel corporation

Mixed Signal Logic Design Engineer

Jul 2022 – Present · 3 yrs 11 mos · Bengaluru, Karnataka, India · On-site

Universal Chiplet Interconnect Express (UCIe) Protocol for Advanced Package
Multi-Gigabit Serializer/Deserializer (SerDes)
Deskew & DCC Calibrations
FIFO
RTL Design and Integration
Responsibilities :
Qualify design to meet power, performance requirements using power simulation and static timing tools.
Work with Pre/Post-silicon verification teams to debug and root-cause RTL simulation/Silicon/FPGA failures.
Provide support to SOC customers for IP integration, debug support and timing convergence.
Scripts to automate design tool flows as required to improve efficiency.

Universal Chiplet Interconnect Express (UCIe)Multi-Gigabit Serializer/Deserializer (SerDes)Deskew & DCC CalibrationsFIFORTL DesignClock Domain Crossing (CDC)+1