Jun 2024 – Present · 2 yrs · Bengaluru, Karnataka, India · On-site

• Project 1 – Level 1 Instruction Cache (L1I)
• Formal Property Verification & Coverage-Driven Sign-off: Led verification of a critical block in the L1I Cache IP from environment setup through formal sign-off. Developed and verified formal properties using Synopsys VC Formal and Cadence JasperGold, ensuring compliance with architectural specifications and uncovering corner-case violations that traditional simulation missed.
• Abstraction & Complexity Reduction Techniques: Implemented multiple abstraction strategies to manage state-space explosion, including replacing design memories with abstract formal models and using symbolic constants for parameterized values. These techniques achieved faster property convergence and enabled verification of deeper design states that were previously unreachable.
• Coverage Analysis : Conducted rigorous coverage analysis to identify over-constraints, dead code, and uncovered logic paths. Systematically debugged coverage gaps, refined assumptions, ultimately achieving formal sign-off quality with comprehensive coverage across all functional scenarios.
• Project 2 – Level 1 Data Cache (L1D)
• Cache Behavior Modeling & End-to-End Verification: Implemented and verified comprehensive checks on read/write operations across diverse request types and memory scenarios. Created abstract formal models of cache hit and miss behavior to simplify state-space complexity while maintaining architectural accuracy, enabling efficient convergence of complex multi-cycle properties.
• Data Integrity & Ordering Validation: Developed scoreboard-based verification techniques to validate data integrity, request ordering, and duplicate detection across the cache hierarchy. Added safety and liveness properties ensuring correct forward progression of transactions and robust end-to-end behavior under all corner-case conditions.