Aarti Prajapati

Product Engineer

Hyderabad, Telangana, India4 yrs 10 mos experience

Highly Stable

Key Highlights

4.7 years of hardware design experience in government sector.
Expertise in RTL Design and Verification methodologies.
Proficient in industry-standard tools and protocols.

Stackforce AI infers this person is a Semiconductor Design Verification Engineer with strong RTL and UVM expertise.

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Skills

Core Skills

Rtl VerificationDesign Verification TestingRtl DesignLeadershipQuality Management

Other Skills

SystemVerilogUVMAMBA protocolsVerilogtiming analysisQuality AssuranceDigital ElectronicsTechnical SupportCross-functional Team LeadershipQuality Assurance ProcessesFPGA prototypingGitXILIXQuestaSimGovernance, Risk Management, and Compliance (GRC)

About

Seeking a Design Verification Engineer role to leverage strong technical expertise and contribute to high-performance semiconductor solutions. M.Tech graduate in VLSI Design with 4.7 years of hardware design experience in the government sector and 1 year of professional training in RTL Design & Verification. Skilled in digital design, timing analysis, FPGA/ASIC flows, and UVM methodology, with hands-on experience in Verilog, SystemVerilog, and verification environments. Proficient in industry-standard tools such as Vivado, Questasim, EDA Playground, Linux, and Git. Knowledgeable in protocols including UART, AXI-4 Lite, APB, and PCIe, with additional exposure to Python scripting.

Experience

4 yrs 10 mos

Total Experience

2 yrs 5 mos

Average Tenure

Current Experience

Electronics corporation of india limited (ecil), department of atomic energy, government of india.

Disign verification engineer

Oct 2025 – Mar 2026 · 5 mos · Hyderabad, Telangana, India · On-site

Verification Engineer with hands-on experience in AMBA protocols (AXI3, AHB-Lite, APB) verification using SystemVerilog and UVM.

SystemVerilogUVMAMBA protocolsRTL VerificationDesign Verification Testing

Vlsi first

RTL Design verification

Aug 2024 – Sep 2025 · 1 yr 1 mo · Hyderabad, Telangana, India

Acquired hands-on experience in timing analysis exercises, focusing on setup, hold, and path delay concepts essential for reliable digital design.
Programmed multiple RTL designs in Verilog, including projects like UART, synchronous counters, and finite state machines using industry-standard simulation tools.
Constructed SystemVerilog testbenches and verified 5+ RTL modules, achieving 95% functional coverage.
Constructed SystemVerilog testbenches with constrained randomization, functional coverage, and assertions to verify complex digital modules.
Conducted UVM-based functional verification, building layered testbench environments and validating DUT behaviour through directed and random simulations.
Conducted UVM-based verification, achieving 0% assertion failures across all simulated DUTs.

VerilogSystemVerilogUVMtiming analysisRTL DesignRTL Verification

Electronics corporation of india limited (ecil), department of atomic energy, government of india.

Technical Officer

Mar 2021 – Jun 2024 · 3 yrs 3 mos

Delivered field support and testing for over 50+ electronic systems across government and industrial sectors, ensuring 99%
uptime during operational periods.
Skills: Leadership, Hardware Design, FPGA, Electronics Manufacturing, Quality Assurance, Digital Electronics, Assembly etc.

LeadershipQuality AssuranceDigital ElectronicsQuality Management