Vikas Makhija

CTO

Noida, Uttar Pradesh, India19 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in multi-die verification and memory protocols.
  • Led a team of over 20 engineers in product development.
  • Strong background in VLSI/EDA with advanced protocol expertise.
Stackforce AI infers this person is a VLSI/EDA expert with strong leadership in memory protocol verification.

Contact

Skills

Core Skills

Functional VerificationMemory Protocols

Other Skills

CommunicationCoachingDDR/LPDDR/HBM/GDDRUCIeSystem VerilogUVMVerification techniquesProduct Development ProcessesDebuggingTest PlanningTechnology ManagementElectrical EngineeringOral CommunicationSocial InfluenceTeam Management

About

Experienced Senior Research And Development Engineering Manager with a demonstrated history of working in the VLSI/EDA industry. Skilled in Functional Verification, Verilog, Working on latest Industry standards like DDR5, LPDDR5 , HBM3 and Expertise in Protocols like DDR, LPDDR, HBM, AXI, Silicon Validation, and RTL Coding. Strong engineering professional with M.tech from Indian Institute of Science .

Experience

19 yrs 11 mos
Total Experience
4 yrs 10 mos
Average Tenure
6 yrs
Current Experience

Synopsys inc

2 roles

Sr. R&D Director

Promoted

Apr 2024Present · 2 yrs 2 mos · Noida, Uttar Pradesh, India

  • Expertise in multi die verification (UCIe)
  • Leading UCIe verification IP design product development from scratch( Protocol layer, D2D adapter, Phy layer)
  • Leading a team of more than 20 engineers
  • Leading multiple Verification IP products
  • Expertise in :
  • Memory Protocols - DDR/LPDDR/HBM/GDDR
  • Layered Protocols - UCIe (Universal Chiplet Interconnect Express
  • System Verilog and UVM
  • Verification techniques
  • Product Development Processes
CommunicationCoachingDDR/LPDDR/HBM/GDDRUCIeSystem VerilogUVM+4

Sr R&D Manager

Jun 2020Apr 2024 · 3 yrs 10 mos · Noida, Uttar Pradesh, India

Synopsys india pvt ltd

2 roles

R&D Manager -II

Jun 2017Jun 2020 · 3 yrs

CommunicationCoaching

R&D Manager

Jan 2016Jun 2020 · 4 yrs 5 mos

CommunicationCoaching

Synopsys

Sr R & D Engineer

Aug 2013Jun 2020 · 6 yrs 10 mos

CoachingDebugging

Qualcomm inc (payroll of mindlance india pvt ltd) delhi

Engineer-III

Mar 2012Aug 2013 · 1 yr 5 mos · New Delhi Area, India

  • Verification, AMBA- AHB,AXI VIP transactor SOC
DebuggingTest Planning

Freescale semiconductors india pvt ltd

2 roles

Senior Design Engineer

Jul 2006Mar 2012 · 5 yrs 8 mos

DebuggingTest Planning

Senior Design Engineer

Jul 2006Mar 2012 · 5 yrs 8 mos

  • SOC Verification, Testbench, Post Silicon Validation,
DebuggingTest Planning

Education

Indian Institute of Science (IISc)

M.tech — CEDT

Jan 2004Jan 2006

YMCA Faridabad

Bachelor of Technology (B.Tech.) — Electronics Engineering

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