K

KARTHIK K.

Product Engineer

India1 yr 1 mo experience

Key Highlights

  • Expert in ASIC Verification and VIP development.
  • Proficient in SystemVerilog and UVM methodologies.
  • Hands-on experience with AMBA protocols.
Stackforce AI infers this person is a Verification Engineer specializing in ASIC design and verification methodologies.

Contact

Skills

Other Skills

Academic PublishingANSYS HFSSVerilogAXIAPBAMBADocumentationRTL DesignSystemVerilogAssertion Based VerificationFunctional VerificationUniversal Verification Methodology (UVM)Regression TestingRegression AnalysisVim

About

Engineer with focus on IP Verification and VIP development. - ASIC Verification. - Development of AXI VIP from scratch. - Development of APB from scratch. - Test plan / Test case /Test bench development at block level. - Hardware Description Languages : Verilog and SystemVerilog. - Good command in writing System Verilog Assertions. - Strong knowledge on Functional Coverage. - Programming Languages : C - Scripting : Python - Methodology Expertise : Universal Verification Methodology (UVM). - Good debugging skills. - Simulation Tools : QuestaSim, VCS, NCSIM - Operating System : Linux, Windows. Protocols Having Hands on Experience. - AMBA AXI - AMBA APB

Experience

1 yr 1 mo
Total Experience
1 yr 1 mo
Average Tenure
--
Current Experience

Università degli studi di siena

Research Fellowship

Jan 2022Mar 2023 · 1 yr 2 mos · Siena, Tuscany, Italy · On-site

Academic PublishingANSYS HFSS

Education

Università di Siena

Master's degree — Telecommunications Engineering

Jan 2017Jan 2021

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