Avinash Yadava

Software Engineer

Hyderabad, Telangana, India4 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Strong foundation in VLSI physical design concepts.
Hands-on experience in Synthesis to Place and Route.
Proficient in TCL scripting for design optimization.

Stackforce AI infers this person is a VLSI Physical Design Engineer with expertise in timing closure and design optimization.

Contact

Skills

Core Skills

Physical DesignStatic Timing AnalysisOptical Design

Other Skills

TCLMatlabFusion ComplierECOPhysical VerificationFloorplanningPlacement and RoutingStarrcRoutingSignal IntegrityPlacementLayout Versus Schematic (LVS)Design Rule Checking (DRC)Timing ClosurePrimetime

About

As a PD Engineer I have developed a strong foundation in VLSI physical design concepts, methodologies, and EDA tools. • Hands-on experience ranges from Synthesis to Place and Route (PNR) and Static Timing Analysis (STA), showcasing my comprehensive understanding of the entire design flow. • Have also applied my skills in TCL scripting to optimize the performance, power & area of the designs.

Experience

4 yrs 5 mos

Total Experience

2 yrs 2 mos

Average Tenure

4 yrs

Current Experience

Chipsolve technologies private ltd

Physical Design Engineer

Jun 2022 – Present · 4 yrs · Hyderabad, Telangana, India · On-site

Physical DesignStatic Timing AnalysisTCL

Vlsiguru training institute

Physical Design Engineer

May 2021 – Jan 2022 · 8 mos · Bengaluru, Karnataka, India · Hybrid

Banaras hindu university

Summer Intern

Apr 2017 – Sep 2017 · 5 mos

Illumination system design using Matlab
Projects included how to use optical design and analysis software while applying principles of optics to the design of their optical, source modeling, displays, daylighting, lights pollution, faceted reflectors, and stray light analysis using Matlab tool

MatlabOptical Design