SANDEEP GAUR

Software Engineer

Coimbatore, Tamil Nadu, India8 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 8+ years in VLSI as IP Verification Engineer
  • Expert in UVM-based verification methodologies
  • Strong knowledge of PCIe and CXL protocols
Stackforce AI infers this person is a VLSI Verification Engineer with expertise in hardware protocols.

Contact

Skills

Core Skills

Ip VerificationFunctional Verification

Other Skills

SystemVerilogUniversal Verification Methodology (UVM)PCIe protocolCXL protocolVerilogMicrosoft OfficeC (Programming Language)C++JavaDebugging

About

I have 8+ years of Experience in VLSI Industry as an IP Verification Engineer. Good in Hardware Description Languages like Verilog , System Verilog. I have a good knowledge in verifying the IP using UVM based Methodology. Currently working in PCIe protocol. Worked in CXL protocol. I have a Protocol knowledge in PCIE Technology which is used as an Interconnect between Devices. Bus Protocol like APB and AXI .

Experience

8 yrs 11 mos
Total Experience
4 yrs 5 mos
Average Tenure
4 yrs 11 mos
Current Experience

Qualcomm

2 roles

Senior Lead Engineer

Promoted

Nov 2025Present · 7 mos

SystemVerilogUniversal Verification Methodology (UVM)PCIe protocolCXL protocolVerilogIP Verification+1

Senior Engineer

Jul 2021Nov 2025 · 4 yrs 4 mos

Mobiveil inc.

Senior IP Verification Engineer

Jul 2017Jul 2021 · 4 yrs · Greater Chennai Area

Education

KSR INSTITUTE FOR ENGINEERING AND TECHNOLOGY, NAMAKKAL

Bachelor of Engineering (BE) — ELECTRONICS AND COMMUNICATION ENGINEERING

Jan 2013Jan 2017

Stackforce found 100+ more professionals with Ip Verification & Functional Verification

Explore similar profiles based on matching skills and experience