Prathamesh Mhabdi — Software Engineer
Contributing to Data Center Engineering group at Marvell. A Design Verification Engineer with 5.5 years of experience in the Processor/CPU domain, specializing in verification of complex processor sub-blocks and functional safety features. My expertise spans verification planning, and coverage closure, with strong proficiency in Assembly programming, SystemVerilog, UVM, and assertions-based verification. At Cadence Design Systems (Tensilica IP), I have contributed to projects such as Dual-Core LockStep (DCLS), Windowed Watchdog Timer (WWDT), and Functional Safety (FuSa) verification for the Xtensa LX8 CPU platform, as well as AXI bus verification, Memory ECC/Parity, and RISC-V traceport and trigger module verification. I have been closely involved in ISO 26262 Functional Safety compliance, authoring technical safety documents, reviewing test plans, and driving certification work products. I’m passionate about building reliable, safety-compliant CPU designs and continuously learning new verification methodologies.
Stackforce AI infers this person is a Semiconductor Verification Engineer with a focus on Functional Safety and Processor Design.
Location: Pune, Maharashtra, India
Experience: 5 yrs 3 mos
Skills
- Functional Verification
- Systemverilog
- Functional Safety
- Universal Verification Methodology (uvm)
Career Highlights
- 5.5 years of experience in Processor/CPU verification.
- Expertise in Functional Safety and ISO 26262 compliance.
- Proficient in advanced verification methodologies like UVM.
Work Experience
Marvell Technology
Staff Engineer (2 mos)
Cadence
Lead Design Engineer (2 mos)
Design Engineer II (3 yrs 5 mos)
Design Engineer I (1 yr 8 mos)
Education
Master of Technology - MTech at BITS Pilani Work Integrated Learning Programmes
Bachelor of Engineering at Vishwakarma Institute of Information Technology
Higher Secondary Certificate at Fergusson College
