Sanjana VK

Software Engineer

Bengaluru, Karnataka, India3 yrs 11 mos experience

Most Likely To Switch

Key Highlights

Specialized in USB protocol IP verification.
Enhanced functionality for USB 2.0 and USB 3.x protocols.
Strong foundation in verification methodologies and digital design.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in USB protocol development.

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Skills

Core Skills

Usb VipIp VerificationSystemverilogTeam Management

Other Skills

UTMI InterfacePIPE InterfaceDebuggingVery-Large-Scale Integration (VLSI)OrCADComstack of AutosarCommunication ProtocolsEmbedded SystemsMicrocontrollersFunctional VerificationApplication-Specific Integrated Circuits (ASIC)Python (Programming Language)AUTOSARIn-Vehicle CommunicationBudget Preparation

About

Verification Engineer with 3+ years experience at Synopsys specializing in USB protocol IP verification — including USB 2.0, EUSB2 (v1 and v2), and USB 3.x VIP development. Currently working at Synopsys on enhancing and maintaining USB VIP , with experience across protocol layer, link layer and PHY-related modeling. My work involves implementing new features, protocol compliance enhancements, debugging complex protocol scenarios, exception injection, controller behavior checking and collaboration with design and testbench teams. Passionate and curious about solving complex protocol verification challenges and continuously expanding expertise in verification methodologies and different protocols.

Experience

3 yrs 11 mos

Total Experience

1 yr 11 mos

Average Tenure

2 yrs 10 mos

Current Experience

Synopsys inc

3 roles

Senior ASIC Digital Design engineer

May 2026 – Present · 1 mo · On-site

USB VIPIP Verification

ASIC Digital Design Engineer

Aug 2023 – May 2026 · 2 yrs 9 mos · On-site

Contributing to the development and enhancement of USB Verification IP (VIP) solutions across USB 2.0, USB 3.x and eUSB2 protocols.
USB 2.0/ EUSB2V2:
Enhanced protocol and link layer functionality for USB 2.0 and eUSB2 VIP.
Contributed to transfer-related features, exception injection and PHY-related modeling.
Applied UTMI interface knowledge for protocol, link and PHY interaction analysis.
USB 3.x:
Implemented protocol and link layer enhancements for USB 3.x VIP.
Analyzed and resolved LTSSM-related issues and protocol behavior during abort and recovery scenarios.
Applied PIPE interface knowledge for Link Layer and PHY interaction analysis.
Cross Functional Contributions:
Performed Host and Device side protocol analysis and debugging across USB VIP, controller and testbench environments.
Added protocol checks and monitoring features to improve controller behavior validation and protocol compliance.
Collaborated with design, verification and VIP teams to implement new features, resolve integration issues and maintain regression quality.
Participated in VIP integration and regression validation activities, performing failure triage and root-cause analysis prior to feature releases.

USB VIPIP VerificationUTMI InterfacePIPE InterfaceDebugging

Intern

Mar 2023 – Aug 2023 · 5 mos · On-site

Built foundational expertise in Digital Electronics, Verilog and System Verilog.
Learned UVM methodology and testbench architecture.
Performed RTL Lint and CDC analysis.
Gained exposure to ASIC verification flows and industry-standard verification methodologies.

SystemVerilogVery-Large-Scale Integration (VLSI)