David Esteban Ortega Figueroa

Product Engineer

Chile3 yrs experience
Highly Stable

Key Highlights

  • Summa Cum Laude graduate in Electronics Engineering.
  • Expert in Signoff EDA tools and digital design closure.
  • Experience in deep learning for medical image analysis.
Stackforce AI infers this person is a Semiconductor Applications Engineer with expertise in digital design and EDA tools.

Contact

Skills

Core Skills

Signoff ToolsEngineering Change Orders

Other Skills

PythonDebuggingPower RecoveryTiming ClosureLinuxTCLVHDLVerilogProblem SolvingMicroelectronicsGitEDA ToolsPrimeClosureDigital IC DesignAprendizaje automático

About

Electronics Engineer graduated Summa Cum Laude from Universidad Industrial de Santander, with a strong background in digital systems, signal processing, and embedded electronics. Currently working as an Applications Engineer at Synopsys Chile, where I support and validate Signoff EDA tools focused on Engineering Change Orders (ECOs), including timing, power recovery, and logic updates. My role involves debugging tool behaviors, automating flows, and creating internal documentation to optimize usability and team productivity. Academically, I was a member of the CPS (Connectivity and Signal Processing) research group, where I gained experience in data processing, scientific reporting, and deep learning applied to medical image analysis. My thesis focused on a methodology for integrating multiple deep learning models for lesion detection in screening mammography, including model benchmarking, saliency analysis, and prediction integration strategies. I am skilled in Python, C++, Verilog, Git, MATLAB, LaTeX, and tools such as Orcad and Office. I value continuous learning, creative problem-solving, and contributing to innovative solutions in the semiconductor industry.

Experience

3 yrs
Total Experience
3 yrs
Average Tenure
3 yrs
Current Experience

Synopsys inc

2 roles

Applications Engineering, Sr Engineer

Promoted

May 2024Present · 2 yrs 1 mo · Santiago Metropolitan Region, Chile

  • Support and validate Signoff tools used in digital design closure, with a strong focus on Engineering Change Orders (ECOs), including power recovery, timing fixes, and functional updates.
  • Perform in-depth debugging of unexpected tool behavior, identifying root causes and working closely with R&D teams to ensure tool reliability.
  • Collaborate with global teams to evaluate tool performance in real-world scenarios and support customer environments.
PythonEngineering Change OrdersDebuggingSignoff ToolsPower RecoveryTiming Closure

Applications Engineering, Engineer

May 2023Apr 2024 · 11 mos · Santiago Metropolitan Region, Chile

PythonEngineering Change Orders

Education

Universidad Industrial de Santander

Bachelor’s Degree in Electronics Engineering — Electronics Engineering

Jan 2018Jan 2023

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