성민 박 — Software Engineer
ASIC physical implementation(PI Front-End) engineer - 10 years of work experience in ASIC implementation design(Exynos development) - Timing / Synthesis for large ASIC design. - Design constraints scripting and maintenance - Synthesis related scripting and maintenance - Timing reporting and design statistics collection - RTL to gates formality verification - Experience in Synopsys, Cadence and other EDA tools(Design Compiler, Fusion Compiler, Primetime, Innovus, EQ, VCLP, GCA, Spyglass, ClockFX, ICC, ICC2) - Handling timing constraints(SDC), DK(Design kit), Logic Synthesis(using DC, DCG, FC), Timing Debugging and ECO(using PT) and UPF(using VCLP) - Experience in a scripting language TCL / Perl / Python
Stackforce AI infers this person is a highly skilled ASIC design engineer with extensive experience in physical implementation.
Location: Seoul, Seoul, South Korea
Experience: 13 yrs 2 mos
Skills
- Asic Physical Implementation
- Eda Tool Expertise
Career Highlights
- 10 years of experience in ASIC design.
- Expertise in timing and synthesis for large ASIC designs.
- Proficient in multiple EDA tools including Synopsys and Cadence.
Work Experience
Synopsys Inc
Application Engineer (2 yrs 6 mos)
삼성전자
Staff Engineer (10 yrs 8 mos)
Education
학사 at Dongguk University
