Prasanth Uppada

Product Engineer

Bengaluru, Karnataka, India7 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in DFT methodologies and ATPG techniques.
Proven track record in scan insertion and boundary scan tests.
Strong leadership experience in team training and project execution.

Stackforce AI infers this person is a DFT Engineer specializing in ASIC design and verification within the semiconductor industry.

Contact

Skills

Core Skills

DftScan InsertionAtpgMbistRtl Design

Other Skills

Fusion compilerGenus stylusrequirement collectionspecification definitionfeature implementationscan executionpost scan checksmulti-clock domain blocksstuck-at faultsat-speed faultspattern portingtiming simulationsdebuggingteam leadershipDesign Compiler

About

Experienced DFT Engineer with knowledge on Boundary SCAN, JTAG 1149.1, Memory BIST tests, scan insertion, ATPG of stuck-at and at-speed tests, and ATPG pattern porting or retargeting. Know-how on RTL design of external interfaces including Parallel Port Interface to speed-up the test booting, and I2C. Hands-on experience on AMBA AHB and AMBA APB protocols. Good engineering professional with B. Tech in Electronics and Communications from Rajiv Gandhi University of Knowledge Technologies (RGUKT), Nuzvid also known as AP IIIT Nuzvid.

Experience

7 yrs 8 mos

Total Experience

2 yrs 6 mos

Average Tenure

4 yrs 10 mos

Current Experience

Nxp semiconductors

DFT Engineer

Aug 2021 – Present · 4 yrs 10 mos · Bengaluru, Karnataka, India

Both Fusion compiler & Genus stylus based scan insertion flow development.
Here the responsibilities include requirement collection from the BLs (NXP internal working groups), specification definition, feature implementation in collaboration with the vendor, scan execution and support.
Post scan checks implementation as a left shift from ATPG that includes all the scan features insertion checks.
Supporting architectures: Flattened scan and hierarchical scan on partition based.

Fusion compilerGenus stylusscan insertionrequirement collectionspecification definitionfeature implementation+3

Cerium systems

DFT Engineer

Jul 2020 – Aug 2021 · 1 yr 1 mo · Bengaluru, Karnataka, India

Worked for Oregon Intel's RFIC
Responsibilities:
1. ATPG of multi-clock domain blocks. Targeted stuck-at and at-speed faults.
2. Block level pattern porting or retargeting to SoC level.
3. ATPG pattern zero-delay & timing simulations and debugging.
4. Led a team of 3 people - Ramped them up on ATPG, helped them in resolving issues and acted as ATPG POC for the client.

ATPGmulti-clock domain blocksstuck-at faultsat-speed faultspattern portingtiming simulations+3

Sevya multimedia

4 roles

DFT Engineer

Aug 2019 – Jun 2020 · 10 mos

Worked at STMicroelectronics client for Test chips. The chips work on 3-clock domains, one is of pad supported frequency for register programming and rest all are from PLL that are controlled by OCC controllers.
Responsibilities:
1. Scan insertion that supports both standard scan and compression.
2. Chip level and block level ATPG of stuck-at and at-speed tests.
3. ATPG pattern simulations with timing and with no timing, and debugging.
Tools: Design Compiler (for Scan insertion) and Tetramax (for ATPG)

scan insertionATPGtiming simulationsdebuggingDesign CompilerTetramax

DFT Engineer

Promoted

Aug 2018 – Jul 2019 · 11 mos

Worked at ADI client for an ARM based SoC of functional safety level ASIL-D. It works on 2 clock domains controlled by OCC controllers.
Responsibilities:
1. Boundary scan tests.
2. Memort BIST tests with SMARCHCHKBvcd, LVMARCHX, LVGALCOLUMN algorithms for RAM testing, READONLY algorithm for ROM testing in tessent LVision flow.
3. SoC level ATPG of stuck-at and at-speed tests for both full scan and compression test modes. Safe state checks at digital to/from analog interface. Achieved 98% stuck-at and 80% at-speed test coverage goals.
4. ATPG pattern simulations and debugging.
5. Controlling of various DFT techniques using JTAG 1149.1.
6. RTL design of Parallel Port Interface that supports up to 32-bit parallel external data transfers in both the directions. Used it to speed-up the test booting compare to usual booting through SPI. Fixed lint and CDC issues, and provided timing constraints.
Used tools: JTV (for BSCAN), Modus (for ATPG) and Tessent MBIST (for MBIST tests)

Boundary scan testsMBIST testsATPGJTAG 1149.1RTL designtiming constraints+2

RTL Design Engineer

May 2018 – Jul 2018 · 2 mos

Developed RTL code for I2C slave interface. It is part of a dedicated ASIC for laser projectors. The register map in the chip is programmed using the I2C slave. The address space is paged, meaning that there are multiple address banks and one of the registers holds current bank number for register access. It is APB compatible.
Used tools: Questasim and Verilator

RTL code developmentI2C slave interfaceASIC designVerilatorQuestasimRTL design