Jaykishan Dudhrejiya

Software Engineer

Bengaluru, Karnataka, India4 yrs 10 mos experience

Key Highlights

Experienced in RTL Verification and Functional Verification.
Proficient in Universal Verification Methodology (UVM) and SystemVerilog.
Staff Engineer with a strong background in ASIC design.

Stackforce AI infers this person is a skilled ASIC Design Verification Engineer with expertise in verification methodologies.

Contact

Skills

Core Skills

Universal Verification Methodology (uvm)

Other Skills

SystemVerilogPerlRTL VerificationAXIPCIeFunctional VerificationVHDLVerilog

Experience

4 yrs 10 mos

Total Experience

2 yrs 2 mos

Average Tenure

5 mos

Current Experience

Marvell technology

Staff Engineer

Jan 2026 – Present · 5 mos · Bengaluru, Karnataka, India · Hybrid

Synopsys inc

Senior Design Verification Engineer

Feb 2024 – Jan 2026 · 1 yr 11 mos · Bengaluru, Karnataka, India · On-site

Einfochips (an arrow company)

2 roles

Asic Design Verification Engineer

Aug 2021 – Feb 2024 · 2 yrs 6 mos · Ahmedabad, Gujarat, India

Universal Verification Methodology (UVM)SystemVerilog

Project Trainee

Jan 2021 – Aug 2021 · 7 mos · Ahmedabad, Gujarat, India

Universal Verification Methodology (UVM)SystemVerilog

Education

Gujarat Technological University (GTU)

Bachelor of Engineering - BE

Jan 2016 – Jan 2020

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