Linumon Thomas

Software Engineer

Bengaluru, Karnataka, India12 yrs 4 mos experience
Highly Stable

Key Highlights

  • Expert in Physical Design and Static Timing Analysis.
  • Implemented low power design methodologies in advanced technologies.
  • Experience with leading companies like ARM, Intel, and Qualcomm.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Analysis.

Contact

LinkedIn

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

PrimetimeSynopsys PrimetimeptecoLogic SynthesisClock Tree SynthesissynthesisPhysical SynthesisPNRfusion compilermanual synthesisstaLow-power DesignCustom Designstiming closurepower convergence

About

Have experience in manual synthesis,physical design,static timing analysis and timing closure .Implemented low power design methodologies in designs with latest nanometer technologies.Scan insertion and DFT were part of design.

Experience

12 yrs 4 mos
Total Experience
2 yrs 1 mo
Average Tenure
1 yr 10 mos
Current Experience

Arm

Physical Design Engineer

Aug 2024 – Present · 1 yr 10 mos · Bangalore Urban, Karnataka, India

Sifive

Physical Design Engineer

Jul 2022 – Aug 2024 · 2 yrs 1 mo · Bengaluru, Karnataka, India

Physical DesignStatic Timing AnalysisPrimetimeSynopsys PrimetimeptecoLogic Synthesis+6

Intel corporation

Digital Design Engineer

Jan 2018 – Jun 2022 · 4 yrs 5 mos · Bangalore

manual synthesisPhysical DesignstaLow-power DesignStatic Timing AnalysisCustom Designs

Qualcomm

STA Engineer

Jul 2017 – Dec 2017 · 5 mos · Bengaluru, Karnataka, India

Intel corporation

Intern

Jul 2016 – Jun 2017 · 11 mos · Bangalore

  • Worked as digital design engineer responsible for synthesis,sta,timing closure and power convergence.Had experience in physical design.

Wipro limited

Project Engineer

Dec 2012 – Aug 2015 · 2 yrs 8 mos · Cochin Area, India

Education

RV College Of Engineering

Master's degree — VLSI and Embedded Sysytem Design

Jan 2015 – Jan 2017

Rajagiri School of Engineering and Technology, Rajagiri Valley P.O, Kakkanad, Kochi- 682 039

Bachelor's degree — Electronics and Communications Engineering

Jan 2008 – Jan 2012

RV College Of Engineering

Master of Technology - MTech — VLSI

Stackforce found 100+ more professionals with Physical Design & Static Timing Analysis

Explore similar profiles based on matching skills and experience

CHANDAN JHA

CHANDAN JHA

Senior Hardware Engineer

at Qualcomm

Bengaluru, India5 yrs 9 mos exp
Physical DesignMicroarchitecture
Allen Nguyen

Allen Nguyen

SOC Physical Design Engineer

at Synopsys Inc

Ho Chi Minh City, Vietnam5 yrs 3 mos exp
Physical DesignApplication-Specific Integrated Circuits (ASIC)
Srinath Jeevakumar

Srinath Jeevakumar

Senior Architect

at NVIDIA

Bengaluru, India6 yrs 8 mos exp
Performance VerificationSilicon Bring-upPerformance Analysis
Swayam Satya Rout

Swayam Satya Rout

Memory Design Engineer

at Texas Instruments India

Bengaluru, India3 yrs 2 mos exp
Very-Large-Scale Integration (VLSI)Digital Electronics
Ashutosh Rao

Ashutosh Rao

R&D Engineer

at Synopsys Inc

Bengaluru, India4 yrs 4 mos exp
Static Timing AnalysisCircuit DesignHardware Security
Nishant Gupta

Nishant Gupta

Senior VLSI Design Engineer

at Sandisk

Bengaluru, India6 yrs 7 mos exp
FPGA IP Software DevelopmentFunctional VerificationDigital DesignsComputer Vision Systems DevelopmentFPGA Implementation
Shivaprasad Boddupally

Shivaprasad Boddupally

Analog Design Engineer

at Sophrosyne Semiconductor

Nalgonda, India4 yrs 4 mos exp
Analog Integrated Circuit DesignElectronic Circuit DesignSilicon Validation
Gaurav Gupta

Gaurav Gupta

Senior R&D Manager

at Synopsys Inc

India14 yrs 6 mos exp
Circuit DesignVerificationSimulationLow Power Design