S

Shiva Shanth Reddy G.

Software Engineer

Bengaluru, Karnataka, India4 yrs 2 mos experience

Key Highlights

  • Experienced in RTL design and development for advanced semiconductor projects.
  • Proficient in PCIe and DMA implementations with strong Verilog skills.
  • Hands-on experience with SDC constraints and RTL verification processes.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and PCIe development.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignDmaPcieRtl Development

Other Skills

RDLSystemVerilogLogic DesignVerilogSimulationsIP-XACTEthernet Mac layerDirect memory accessCDCLintVerdiFunctional SpecificationsRTL CodingDebugging CodeField-Programmable Gate Arrays (FPGA)

Experience

4 yrs 2 mos
Total Experience
1 yr 9 mos
Average Tenure
6 mos
Current Experience

Qualcomm

Senior Engineer

Dec 2025 – Present · 6 mos

Krutrim

RTL Design Engineer

Dec 2024 – Dec 2025 · 1 yr · Bangalore Urban, Karnataka, India · On-site

  • Worked on the implementation of DMA engine and Ethernet Mac layer.
  • Created SDC constraints and also RDL file.
  • Did the Lint, Compile checks also and added the RTL SVA.
RDLSystemVerilogRTL DesignDMA

Aisemicon

2 roles

RTL Design Engineer

Promoted

Sep 2022 – Nov 2024 · 2 yrs 2 mos · Bengaluru, Karnataka, India

  • Worked on PCIe for RTL development with micro architecture of LTSSM in physical layer mainly on detection of remote device, link negotiation, changing speed of the link and link equalization mechanism.
  • Built the communication between MAC and serdes.
  • Generation of TLP, DLLP(appending framing tokens,CRC generation) and arbitration between data and ordered sets.
  • Good knowledge on Flow control in link layer.
  • Worked on UART and APB.
  • Have knowledge on AXI and APB.
Logic DesignVerilogPCIeRTL Development

Associate Design Engineer

Feb 2022 – Aug 2022 · 6 mos · Bengaluru, Karnataka, India

VerilogSimulations

Education

Chaitanya Bharathi Institute Of Technology

Bachelor's degree

Jan 2015 – Jan 2019

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