Abhay Patil — Product Engineer

🚀 Chip Design Engineer Extraordinaire | Turning Concepts into Cutting-Edge Realities Hey there! I'm Abhay Patil, a passionate electronics and communication specialist with a knack for turning ideas into reality through the intricate world of Physical Design and Verification. Education: Graduated from S G Balekundri Institute of Technology, specializing in Electronics and Communication. Training: Completed an intensive six-month training course at Entuple Technologies Pvt Ltd, specializing in Physical Design and Verification. Expertise: Skilled in RTL to GDSII full flow across multiple technology nodes: 180nm, 45nm, and advanced 7nm. Skills Acquired: Proficient in Verilog HDL, synthesis, post-synthesis STA, MMMC Flow, physical design essentials including floorplanning, power planning, placement, and routing. Project Experience: Led the transformation of an 8-bit Counter from RTL to GDSII. Contributed to diverse projects like ASP, UART, DTMF, and MSP430, showcasing expertise in synthesis, post-synthesis STA, and complete GDSII flow. Notable Achievements: Managed the physical design aspects of the Leon processor, handling floorplanning, power planning, and conducting timing-aware analysis for over 20 macros with relative floorplans. Current Focus: Actively engaged in synthesizing the MSP430 for the 45nm technology node, targeting a clock frequency of 1GHz. Responsibilities include post-synthesis STA and ongoing physical design floorplanning. Passion and Drive: Motivated by the ever-evolving semiconductor technology landscape and passionate about translating ideas into intricate chip designs.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in Physical Design and Verification.

Location: Bengaluru, Karnataka, India

Experience: 0 mo