Kranthi Kandula

Operations Associate

Hyderabad, Telangana, India10 yrs 11 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Silicon Lifecycle Management and DFT solutions.
Proven leadership in developing innovative silicon test solutions.
Strong background in design validation and functional testing.

Stackforce AI infers this person is a Semiconductor expert with a focus on Silicon Lifecycle Management and DFT solutions.

Contact

Skills

Core Skills

Silicon Lifecycle ManagementDfxDftSilicon DebugOnchip Performance MonitoringTesting SolutionsDesign ValidationTestingFunctional ValidationDft Testing

Other Skills

Silicon TestDebugMonitoringHigh Speed Access TestAutomotive In-system ControllerInfield MonitoringStructural MonitorsOnchip Performance MonitorHigh Bandwidth In-System TestingQuality AssessmentHigh Bandwidth TestingSCAN FeaturesPattern GenerationTest Plan CreationDFT Architecture

About

DFT/DFx Manager involved in the development and deployment of new forward looking solutions High speed access, Automotive , Insystem test solutions, Silicon Lifecycle Management (SLM). Have extensive experience in micro-architect, design, development of Test and Debug Solutions.

Experience

10 yrs 11 mos

Total Experience

3 yrs 7 mos

Average Tenure

7 yrs 2 mos

Current Experience

Synopsys inc

5 roles

Senior Manager

Promoted

May 2026 – Present · 1 mo

Manager

Feb 2023 – Apr 2026 · 3 yrs 2 mos

Leading SLM (Silicon Lifecycle Management) Design and DFx team involved in developing new/forward-looking solutions in silicon test,
debug and monitoring. (Monitors- Performance monitor, PVT, High Speed Access Test (USB/PCIe, IEEE 1149.10), Test Access- AIT Automotive In-system Controller)

Silicon Lifecycle ManagementDFxSilicon TestDebugMonitoring

Staff Engineer

Jul 2022 – Jan 2023 · 6 mos

Leading SLM (Silicon Lifecycle Management) Design and DFx team involved in developing new/forward-looking solutions in silicon test,
debug and monitoring. (Monitors- Performance monitor, PVT, High Speed Access Test (USB/PCIe, IEEE 1149.10), Test Access- AIT Automotive In-system Controller)

Silicon Lifecycle ManagementDFxSilicon TestDebugMonitoring

Sr R&D Engineer II

Dec 2020 – Jun 2022 · 1 yr 6 mos

SLM Design team lead involved in developing new forward-looking solutions in DFT test, silicon debug and infield monitoring.
Structural Monitors- Path Margin Monitor,
Process Voltage Temperature (PVT)
High Speed Access Test (USB/PCIe, IEEE 1149.10)
DFT - SEQ , XLBIST
DFx Test Access- AIT (Automotive In-system Controller), SHS network

DFTSilicon DebugInfield MonitoringStructural MonitorsHigh Speed Access Test

Sr R&D Engineer I

Dec 2018 – Nov 2020 · 1 yr 11 mos

1. Solution Architect for SLM Onchip Performance Monitor
https://www.synopsys.com/solutions/silicon-lifecycle-management.html
2. Solution Architect for TestMAX SLT that allows to preform high bandwidth in-system
testing and diagnosis at system level using high-speed functional interfaces such as a
USB/PCIe. (Patent pending)
https://www.synopsys.com/implementation-and-signoff/test automation/testmax-ale.html
3. Worked on Quality Assessment of XLBIST , DFTMAX SEQ HW designs.

Onchip Performance MonitorHigh Bandwidth In-System TestingQuality AssessmentOnchip Performance MonitoringTesting Solutions

Amd

2 roles

Sr Design Engineer

Promoted

Jul 2018 – Dec 2018 · 5 mos

Worked on design validation of SCAN features and Single chain mode (SCM) trace,
Patterngeneration, RBM models.
Clock stop sequence generation and SCAN DUMP.

Design ValidationSCAN FeaturesPattern GenerationTesting

Design Engineer 2

Jul 2015 – Jun 2018 · 2 yrs 11 mos

Worked on creating Test plan environment and testcases for functional validation of
DFT Architecture, components IEEE1149.1, 1687, 1500, BSCAN, SCAN, MBIST, BIST, Clock Observation.
Responsible for DVT test pattern generation Environment setup, maintenance and Bootup Sequence for
DFT verification.
Worked on generating validation patterns for BSCAN, SCAN Network, PHY loopback, Clock observation.

Test Plan CreationFunctional ValidationDFT ArchitectureDFT Testing