Seonki Hong

Software Engineer

Seongnam, Gyeonggi, South Korea3 yrs 7 mos experience
Highly Stable

Key Highlights

  • Expert in RTL-to-GDS flow optimization
  • Led technology enablement for HBM4/4E
  • Collaborated with top industry leaders
Stackforce AI infers this person is a Semiconductor expert with a focus on EDA and physical design.

Contact

Skills

Core Skills

Physical DesignEdaAuto P&rPpa

Other Skills

Physical implementationFusion CompilerICC2Technology enablementASICDTCOPPA evaluationLinuxVLSI

About

Staff R&D Engineer | Digital Implementation (RTL-to-GDS) | Fusion Compiler & ICC2 As a R&D(Product) Engineer of Fusion Compiler at Synopsys, I specialize in delivering optimized, automated EDA solutions and driving fundamental enhancements for Fusion Compiler. My expertise lies in navigating the complexities of the RTL-to-GDS flow, with a particular focus on Auto P&R and PPA (Power, Performance, Area) optimization for next-generation silicon. I have been collaborating with global industry leaders, including Samsung S.LSI, Samsung Memory, SK Hynix and Google, to resolve critical design bottlenecks and enable cutting-edge technology nodes. — Expertise — • Full RTL-to-GDS Flow: Troubleshooting and technical support across the digital implementation domain. • PPA & Convergence: Driving PPA push and ensuring DRC convergence for high-performance designs. • Technology Enablement: Evaluating and enabling emerging nodes and library readiness. • Strategic Collaboration: Facilitating seamless communication between R&D, PE, and AE teams to accelerate feature deployment and version migration. — Experience — : Project with below companies. • Samsung Memory (2024.05 – Present): Leading the HBM4/4E technology enablement via new Auto P&R feature developement. • Samsung S.LSI (2023.02 – Present): Spearheading Advanced Node DTCO and PPA evaluation on cutting-edge process nodes. • Google (2023.08 – 2024.03): PPA push and Physical DRC convergence for Out-of-the-Box (OOTB) solutions. • ARM Library readiness (2024.02 – 2024.06): Evaluated Fusion Compiler readiness and resolved design issues for ARM libraries on emerging nodes ahead of production. — Technical Proficiency — • Primary Tools: Fusion Compiler, IC Compiler II (ICC2) • Specialties: Auto P&R feature enablement, Design Technology Co-Optimization (DTCO), Library Evaluation, Flow/Feature Testing.

Experience

3 yrs 7 mos
Total Experience
3 yrs 7 mos
Average Tenure
3 yrs 7 mos
Current Experience

Synopsys inc

4 roles

Staff R&D Engineer

Promoted

May 2026Present · 1 mo

  • Digital Implementation PE Team
  • Fusion Compiler
  • ICC2
  • RTLIIGDS Flow enablement
Physical designPhysical implementationEDAFusion CompilerICC2

Sr R&D Engineer

Promoted

Feb 2025May 2026 · 1 yr 3 mos

  • Digital Implementation PE team
  • Fusion Compiler
  • ICC2
EDAPhysical designPhysical implementationASIC

R&D Engineer

Nov 2022Feb 2025 · 2 yrs 3 mos

  • Digital Implementation PE team
  • RTLIIGDS Enablement
  • Fusion Compiler
  • ICC2
ASICLinuxEDAPhysical implementationPhysical design

Internship Trainee

Jun 2022Nov 2022 · 5 mos

ASICLinuxEDA

Education

Sungkyunkwan University

Bachelor's degree — Electronic and Electrical engineering

Feb 2022Present

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