Seonki Hong — Software Engineer
Staff R&D Engineer | Digital Implementation (RTL-to-GDS) | Fusion Compiler & ICC2 As a R&D(Product) Engineer of Fusion Compiler at Synopsys, I specialize in delivering optimized, automated EDA solutions and driving fundamental enhancements for Fusion Compiler. My expertise lies in navigating the complexities of the RTL-to-GDS flow, with a particular focus on Auto P&R and PPA (Power, Performance, Area) optimization for next-generation silicon. I have been collaborating with global industry leaders, including Samsung S.LSI, Samsung Memory, SK Hynix and Google, to resolve critical design bottlenecks and enable cutting-edge technology nodes. — Expertise — • Full RTL-to-GDS Flow: Troubleshooting and technical support across the digital implementation domain. • PPA & Convergence: Driving PPA push and ensuring DRC convergence for high-performance designs. • Technology Enablement: Evaluating and enabling emerging nodes and library readiness. • Strategic Collaboration: Facilitating seamless communication between R&D, PE, and AE teams to accelerate feature deployment and version migration. — Experience — : Project with below companies. • Samsung Memory (2024.05 – Present): Leading the HBM4/4E technology enablement via new Auto P&R feature developement. • Samsung S.LSI (2023.02 – Present): Spearheading Advanced Node DTCO and PPA evaluation on cutting-edge process nodes. • Google (2023.08 – 2024.03): PPA push and Physical DRC convergence for Out-of-the-Box (OOTB) solutions. • ARM Library readiness (2024.02 – 2024.06): Evaluated Fusion Compiler readiness and resolved design issues for ARM libraries on emerging nodes ahead of production. — Technical Proficiency — • Primary Tools: Fusion Compiler, IC Compiler II (ICC2) • Specialties: Auto P&R feature enablement, Design Technology Co-Optimization (DTCO), Library Evaluation, Flow/Feature Testing.
Stackforce AI infers this person is a Semiconductor expert with a focus on EDA and physical design.
Location: Seongnam, Gyeonggi, South Korea
Experience: 3 yrs 7 mos
Skills
- Physical Design
- Eda
- Auto P&r
- Ppa
Career Highlights
- Expert in RTL-to-GDS flow optimization
- Led technology enablement for HBM4/4E
- Collaborated with top industry leaders
Work Experience
Synopsys Inc
Staff R&D Engineer (1 mo)
Sr R&D Engineer (1 yr 3 mos)
R&D Engineer (2 yrs 3 mos)
Internship Trainee (5 mos)
Education
Bachelor's degree at Sungkyunkwan University