Mei-Cheng Huang

Director of Engineering

Los Gatos, California, United States29 yrs 5 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in mixed signal and high-speed PHY verification.
Proficient in various verification methodologies.
Extensive experience in ASIC and FPGA verification.

Stackforce AI infers this person is a highly skilled ASIC and FPGA verification engineer with extensive experience in functional verification.

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Skills

Core Skills

Functional VerificationAsic

Other Skills

RTL designVerifying networking FPGAsCreating testbenchWriting direct/random testsVerifying video editing ASICVerilogWriting transactors in VerilogSystemVerilogFPGATCLDebuggingPCIeICMixed SignalOpen Verification Methodology

About

Manage Front-end design verfication , timing and ATPG team. Verification testbench/flow development with UVM, OVM, System Verilog, C++, Verilog, Perl and Python. SNPS Formal verfication on Register verfication and connecitivty. Mixed Signal verification with VCS+NANOSIM on spice netlist, VCS+XA on spice netlist and VCS+XA on VAMS/RNM model High speed PHY verification including LPDDR5X/5/4/3, DDR4/3/2, GDDR5 , HT/ PCIE PHY, and FBDIMM Various Verification methodologies including RTL pre-progressor, CDC tool, RTL X-propagation, linting tools and gate-level simulation. Verification experience with network switch/router ASIC and FPGA Verification experience with video editing ASIC chips.

Experience

29 yrs 5 mos

Total Experience

7 yrs 5 mos

Average Tenure

11 yrs 7 mos

Current Experience

Synopsys inc

5 roles

R&D Sr. Director

Promoted

Feb 2024 – Present · 2 yrs 4 mos

R&D Director

Promoted

Oct 2021 – Feb 2024 · 2 yrs 4 mos

Senior Engineer Manager

Jun 2018 – Sep 2021 · 3 yrs 3 mos

Senior Staff ASIC design Engineer

Promoted

Jul 2015 – Jun 2018 · 2 yrs 11 mos

Staff ASIC Design Engineer

Sep 2014 – Jun 2015 · 9 mos

Advanced micro devices

SMTS

Jan 2002 – Sep 2014 · 12 yrs 8 mos

Intrinsix corp.

Consultant Engineer

Feb 1998 – Apr 2002 · 4 yrs 2 mos

Intrinsix Corp., Nashua, MA 11/01 to 04/02
Responsible for RTL design for I2C protocol to program a network device and lab bring-up
Intrinsix Corp., Chelmsford, MA 3/00 to 10/01
Responsible for verifying networking FPGAs, creating testbench for single/multiple FPGAs, and writing direct/random tests.
Intrinsix Corp., Acton, MA 3/99 to 2/00
Responsible for verifying networking AISCs through direct/random tests
in Tcl, bug fixing on testbench/transactors in Verilog, running/analyzing code
coverage with HDL Score and doing gate simulation
Intrinsix Corp., Marlboro, MA, 5/98 to 2/99
Responsible for verifying video editing ASIC, participating part of
Testbench setup in Perl, writing majority of transactors in verilog, writing
Several behavior modules in c, writing direct/random tests in Perl, running/analyzing code coverage
Intrinsix Corp., Nashua, NH 2/97 to 4/98
Responsible for writing Perl scripts of Wave Driver Transator and Wave
Monitor Transator for Acquisition Process (AP ASIC).

RTL designVerifying networking FPGAsCreating testbenchWriting direct/random testsVerifying video editing ASICFunctional Verification+1

Cabletron systems

Hardware Engineer II

Sep 1996 – Dec 1997 · 1 yr 3 mos

Cabletron Systems Inc., Merrimack, NH 5/97 to 12/97
Responsible for simulating the Host Processor Supplement (HOPS ASIC) in
diagnostic mode and Packet Memory Manager in functional mode and writing
part of simulation plan.
Cabletron Systems Inc., Nashua, NH 9/96 to 4/97
Responsible for design of an Ethernet wire daemon (packet generator and verifier) for G-bit Ethernet Switch, simulating G-Bit Ethernet MAC in system level and design of a SRAM module and a statistics module. Both SRAM and statistics module are simulated and verified in behavior and gate level.