Feb 2018 – Dec 2018 · 10 mos · Bangalore

• AI/EmbeddedSystems/DeepLearning

Feb 2007 – Feb 2018 · 11 yrs · Greater Hyderabad Area

• Process-Aware (PA) circuit design using PA compact models
• Parameter extraction strategies for BSIM3/4, VBIC99, PSP compact models
• Algorithms for Optimization problems
• ESD Modeling and Simulation (Device + Circuit Level)
• TSV based 3D IC stress/failure analysis
• High Power/Voltage LD-HV-MOS/IGBT devices (Si/SiC based) modeling/simulation

Nov 2005 – Jan 2007 · 1 yr 2 mos · Bangalore, India

• Device Modeling: Worked on various compact model (PDKs) generation projects ranging from 150 nm to 65 nm CMOS/SONOS technologies. Created new models for special devices to perform circuit simulation. Project leader for one of the high voltage modeling projects.
• TCAD Calibration and Optimization: Calibration of 65 nm CMOS technology using Taurus TCAD tools. Optimization of process to reduce the leakage current/power.
• Silicon Characterization: Experienced in electrical characterization of E-TEST
• modules. Performed measurements at wafer level (both active and passive devices) to get the required data for compact model generation.