VietHuy Nguyen

DevOps Engineer

Da Nang City, Vietnam2 yrs 5 mos experience

Highly Stable

Key Highlights

Over 2.5 years of experience in Analog Layout.
Expertise in TSMC and Intel technologies.
Proven track record in high-speed data transaction designs.

Stackforce AI infers this person is a Semiconductor Design Engineer with a focus on Analog Layout and Verification.

Contact

Skills

Core Skills

Analog LayoutCustom CompilerSystemverilog

Other Skills

TSMC 3nmTSMC 2nmIntel 18ATSMC 5nmLogic SynthesisScan InsertionATPGTechnical SupportGuide taskWork ManagementTeamworkAPB ProtocolAutomatic Test Pattern Generation (ATPG)Functional VerificationCisco Webex Meetings

About

2,5+ years of experience in Analog Layout. Technode: TSMC N5/N3P/N2 and Intel 18A.

Experience

2 yrs 5 mos

Total Experience

2 yrs 5 mos

Average Tenure

2 yrs 5 mos

Current Experience

Synopsys inc

3 roles

Analog Layout Design, Sr Engineer

May 2026 – Present · 1 mo · Da Nang City, Vietnam · On-site

Analog Layout Design Engineer

Dec 2023 – Apr 2026 · 2 yrs 4 mos · Da Nang City, Vietnam · On-site

Working on UCIE Gen2,3 projects:
TSMC 3nm, 2nm: RX, RXCKTRK blocks.
Intel 18A: DCD block.
TSMC 5nm: Voltage Regulator block.

Custom CompilerAnalog Layout

Digital Design Intern

Jun 2023 – Dec 2023 · 6 mos · Da Nang City, Vietnam · On-site

Project: Design the Delay-Locked Loop Training for High-Speed Data Transaction.
My role (+2 other members): Design from Specification -> RTL -> Verification -> Synthesis/STA/FM -> Scan Insertion/Build ATPG model for stuck-at fault.
Introduction: The DLL is used to create a delayed version of clock signal. The DLL Training (our project) is the training system which is used to control the DLL with the purpose of finding out the optimal data point.
Result:
+ The functionalities of design meet the specification.
+ The code coverage reaches 100% with some exclusion cases (design intention).
+ No set-up timing violation.
+ All Flip-Flops are converted into scan Flip-Flop and added into scan chains.
+ The ATPG stuck-at fault coverage is 99.69%

SystemVerilogLogic Synthesis