Richu Jose Cyriac

Software Engineer

Bengaluru, Karnataka, India11 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 11 years in semiconductor layout and design.
Expert in advanced-node library development and automation.
Proven track record in physical verification and architecture exploration.

Stackforce AI infers this person is a Semiconductor Design Engineer specializing in advanced-node library development and physical verification.

Contact

Skills

Core Skills

Advanced Standard Cell DevelopmentLayout AutomationStandard Cell DevelopmentLibrary DevelopmentLibrary Validation

Other Skills

Advanced-node library developmentProject planningArchitecture explorationPhysical verificationScriptingSynopsys ICVTCL scriptingSkill DevelopmentOptimizationLEF verificationPNR verificationArea reductionStandard cell libraries designValidationPre-sales layout works

About

Semiconductor Layout and DTCO Engineer with 11+ years of experience in advanced standard cell library development, custom layout design, physical verification, and layout automation across Intel, Samsung, TSMC, and Rapidus foundry technologies from 180nm to 2nm nodes. Experienced in architecture exploration, PPA optimization, Synopsys ICV verification deck creation, and advanced-node library development using Cadence Virtuoso, ICV, Tcl, SKILL, Python, and Shell scripting. Currently working on cutting-edge DTCO and advanced-node methodologies with strong focus on scalable automation, physical verification, and research-oriented semiconductor enablement. Areas of Interest: • Standard Cell Architecture • Automation for productivity improvement • Deck creations for enhanced quality

Experience

11 yrs 7 mos

Total Experience

3 yrs 10 mos

Average Tenure

4 yrs 6 mos

Current Experience

Synopsys inc

3 roles

A&MS Senior Staff Layout Design Engineer

Promoted

Apr 2026 – Present · 2 mos · Bengaluru · On-site

Worked on advanced-node library development across leading fabs
Development of BASE/HPC/MBFF/COMB MBFF/POK/ECO/PHYSICAL libraries.
Team lead (team size:20), handled responsibilities of project plan preparation, tracking the updates, reviewing and releasing of these libraries.
Project planning, Architecture exploration, cellchk enablement, layout release, and cross-functional collaboration.
Developed architecture verification decks in Synopsys ICV with ~600 checks for standard cell quality validation across multiple tech nodes enhanced the coding productivity by 20 % using internal tool copilot.
Automated layout generation and library porting with same horizontal metal tracks and different cpp using custom compiler-based TCL scripting with ~95% cells without manual fixes, enhanced the coding productivity by 20 % using internal tool copilot.
Architecture file definition the constraints for internal layout generation tool and enhancements based on technologies and library constraints with a success rate of 60 % of cells without manual intervention.
DTCO activities
Scripting
Custom compiler-based TCL
Metal variant creation, Fractional drive creation
Pin Access and power grid visualizer.
Layout migration for different libraries across multiple technologies.
ICV deck creation for standard cell architecture verification
Layout quality verification decks in ICV.

Advanced-node library developmentProject planningArchitecture explorationLayout automationPhysical verificationScripting+3

A&MS Staff Layout Design Engineer

Promoted

Dec 2023 – Apr 2026 · 2 yrs 4 mos · Bengaluru · On-site

A&MS Layout Design Engineer Sr I

Dec 2021 – Dec 2023 · 2 yrs · Bengaluru · On-site

Skill DevelopmentOptimization

Sankalp semiconductor

Senior Engineer I

Jan 2020 – Dec 2021 · 1 yr 11 mos · Bengaluru · On-site

Worked on older nodes automotive grade library development with clients Microchip and Texas Instruments
TSMC: 180nm, 130nm
Client: Texas Instruments
Support lead for 5 libraries (team size:5), handled responsibilities of project plan preparation, tracking the updates, review and release of these libraries.
Area reduction and porosity improvement for the existing cells
LEF verification & pnr verification activities.
Client: Microchip
Improved contact density to achieve 40% at chip level for automotive grade libraries.
SKILL
Checks for validating architecture compatibility of standard cell
Area, Number of tracks used check for entire standard cell library
Codes for layout creation easiness using bindkeys
SHELL
Extracting data from log files and report files
Codes for giving repeated tasks through automation

Library developmentProject planningLEF verificationPNR verificationStandard Cell DevelopmentLibrary Development

Zia semiconductor pvt ltd

2 roles

Layout Design Engineer II

Promoted

Nov 2017 – Jan 2020 · 2 yrs 2 mos

Designed and validated standard cell libraries in 22nm, 40nm, 14nm,16nm technologies for clients ARM, NXP and ST Microelectronics.
Client: ARM
TSMC 22nm(6.5 T ),16nm(7T library), SAMSUNG 14nm(7T library)
Development and validation of complex combinational cells, Sequential cells, Level Shifters
Pre-sales layout works
Study on possibility of merged active region for standard cells in 16nm tsmc
Study of M2 removal for a specific customer requirement in GF 28nm
Validation of standard cell libraries with different pdk updates
Porting and validation of standard cell libraries for different customers
Client: NXP
TSMC 40nm(9T)
Development and validation of complex combinational cells, Sequential cells, Level Shifters, multibit cells.
Client: ST Microelectronics
TSMC 40nm (SP SRAM Memory compiler)
DRC, DFM and LVS fixes at the leaf cell & Top level.