Aditya Singh — Software Engineer

>M.Tech in VLSI Design from NIT Jalandhar. >Expertise in scan insertion for both uncompressed and compressed architectures, along with On-Chip Clock Controller (OCC) insertion. >Hands-on experience in ATPG pattern generation and simulation for stuck-at and at-speed faults, ensuring high fault coverage. >Proficient in debugging ATPG DRC violations, including chain trace failures, and resolving testability issues. >Experience in test coverage analysis and enhancement, including identification and closure of coverage gaps. >Good exposure to Gate-Level Simulation (GLS), including both zero-delay and SDF-based timing simulations for validating test patterns. >Hands-on experience in Memory BIST (MBIST) implementation, including pattern generation, simulation of basic MBIST operations, ICL, BISR chain verification, and memory repair pattern validation. >Strong working knowledge of JTAG, Embedded Deterministic Test (EDT), Scan Streaming Network (SSN), MBIST, and ATPG architectures. >Proficient with industry-standard DFT and EDA tools, including Tessent (Mentor Graphics), Synopsys VCS, and Cadence Xcelium for simulation and verification. >Experience in DFT linting and RTL testability analysis using tools such as JasperGold and SpyGlass. >Hands-on understanding of the complete ASIC design flow, from RTL design to GDSII, with emphasis on DFT integration. >Experience in RTL synthesis and analysis using Synopsys Design Compiler and Cadence Genus. >Basic understanding of Static Timing Analysis (STA) and Engineering Change Orders (ECO) in synthesized designs. >Good knowledge of Verilog HDL and scripting for automation and debug. >Strong academic foundation in Digital Logic Design, Analog Design, VLSI System Design, and Low Power Design concepts.

Stackforce AI infers this person is a Semiconductor DFT Engineer with expertise in test methodologies and VLSI design.

Location: Noida, Uttar Pradesh, India

Experience: 6 yrs 6 mos