Dileep Ravva

Software Engineer

Hyderabad, Telangana, India14 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in ASIC and VLSI design methodologies.
  • Proficient in Functional Verification and Debugging.
  • Strong background in SystemVerilog and UVM.
Stackforce AI infers this person is a VLSI and ASIC design expert with a focus on functional verification.

Contact

LinkedIn

Skills

Core Skills

Functional VerificationAsic

Other Skills

UVMSystemVerilogVLSISoCDebuggingVery-Large-Scale Integration (VLSI)System on a Chip (SoC)Application-Specific Integrated Circuits (ASIC)VerilogPerlCLinuxC (Programming Language)Open Verification MethodologySilicon Validation

Experience

14 yrs 5 mos
Total Experience
3 yrs 7 mos
Average Tenure
8 yrs 7 mos
Current Experience

Synopsys inc

4 roles

ASIC Digital Design Engineer, Sr Staff

Promoted

Feb 2025 – Present · 1 yr 4 mos · Hyderabad, Telangana, India

UVMSystemVerilogFunctional VerificationVLSISoCASIC+13

ASIC Digital Design Engineer, Staff

Feb 2024 – Jan 2025 · 11 mos · Hyderabad, Telangana, India

ASIC Digital Design Engineer, Sr2

Dec 2020 – Jan 2024 · 3 yrs 1 mo · Hyderabad, Telangana, India

ASIC Digital Design Engineer, Sr1

Aug 2017 – Nov 2020 · 3 yrs 3 mos · Hyderabad, Telangana, India

Cerium systems

Sr Verification Engineer

Jul 2016 – Jul 2017 · 1 yr · Bengaluru, Karnataka, India

Atmel corporation

Verification Engineer

Apr 2013 – Jun 2016 · 3 yrs 2 mos · Chennai, Tamil Nadu, India

Kpit

Member Technical Staff

Jul 2011 – Mar 2013 · 1 yr 8 mos · Bangalore

Education

Birla Institute of Technology and Science, Pilani

Master of Technology - MTech — Microelectronics

Kakatiya University

Bachelor of Technology - BTech — Electronics and Instrumentation

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