Stabin S — Software Engineer

RTL Design Engineer with 5+ years of experience in front-end design and static verification. I’ve worked on multiple SoCs and IPs at Intel and Qualcomm, focusing on RTL development, integration, and signoff. Currently at Synopsys, I specialize in static tools like CDC, Lint, and RDC, helping top semiconductor teams achieve clean and reliable designs. With deep expertise in RTL, static analysis, and debug, I bridge design and verification to deliver first-time-right silicon. 🔧 Skills: RTL Design · Static Verification (CDC, Lint, RDC) · Verilog/SystemVerilog · SoC Integration · Design Signoff

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and static verification.

Location: Chennai, Tamil Nadu, India

Experience: 5 yrs 8 mos