Suresh V

CEO

Bengaluru, Karnataka, India19 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 19+ years of experience in EDA product development.
  • Expertise in Low Power Solutions and Verification.
  • Architect at Synopsys with a focus on UPF solutions.
Stackforce AI infers this person is a seasoned EDA professional specializing in low power design and verification.

Contact

LinkedIn

Skills

Core Skills

EdaLow-power Design

Other Skills

UPFComputer ScienceFPGALow power EmulationLow power FPGAStatic Low power verificationVCS Low power simulationVCSMulti voltage simulationLow power analysisAPFLow power solutionsCC++Unix

About

Specialties: 19+ years of EDA (Electronic Design Automation) product development in Emulation / FPGA / Simulation/ Static verification based Low Power Solutions, ML, Unified Power Format ( UPF ) , Common Power Format ( CPF ) , C/C++

Experience

19 yrs 3 mos
Total Experience
9 yrs 7 mos
Average Tenure
18 yrs 5 mos
Current Experience

Synopsys inc

8 roles

Architect

Promoted

May 2026 – Present · 1 mo

  • Working on UPF solution.
UPFEDALow-power Design

Principal Engineer

Feb 2024 – Apr 2026 · 2 yrs 2 mos

Senior Staff R&D Engineer

Nov 2020 – Jan 2024 · 3 yrs 2 mos

  • Working on FPGA (HAPS) Solution.
Computer ScienceEDA

Staff R&D Engineer

Jun 2017 – Oct 2020 · 3 yrs 4 mos

  • Worked on Low power Emulation (Zebu) and Low power FPGA (Haps) solutions.

Senior R&D Engineer - II

Jun 2014 – May 2017 · 2 yrs 11 mos

  • Worked on Static Low power verification (VC-LP) and VCS Low power simulation (VCS-LP) solutions.

Senior R&D Engineer - I

Promoted

Jun 2011 – May 2014 · 2 yrs 11 mos

  • Worked on VCS Low power UPF based solutions.

R&D Engineer - II

Jun 2009 – May 2011 · 1 yr 11 mos

  • Worked on Multi voltage simulation product (MVSIM).
  • Performance improvement.
  • Low power analysis in frontend.

R&D Engineer - I

Jun 2007 – May 2009 · 1 yr 11 mos

  • Worked on APF based low power solutions. (MVSIM , MVDBGEN, MVCMP)

Archpro design automation (acquired by synopsys)

Software Engineer

Jul 2006 – May 2007 · 10 mos · Bangalore

  • Worked on building parser for Archpro Power Format ++.

Education

Indian Institute of Management, Calcutta

Executive General Management Program

Jun 2023 – Jun 2024

Indian Institute of Science (IISc)

PG Level Advanced Certification Programme in VLSI Chip Design

Jun 2022 – Feb 2023

College of Engineering, Guindy

BE — Computer Science and Engineering

Jan 2002 – Jan 2006

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