R

Rijo John Zachariah

Product Engineer

Bengaluru, Karnataka, India7 yrs 9 mos experience
Highly Stable

Key Highlights

  • Over 7.5 years in digital design engineering.
  • Expertise in microarchitecture and RTL design.
  • Proficient in assertion-based verification and functional coverage.
Stackforce AI infers this person is a Digital Design Engineer specializing in ASIC and VLSI technologies.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignMicroarchitecture

Other Skills

Microarchitecture developmentLintSynthesisAssertion based verificationCode coverageFunctional coverageLogic SynthesisData Structures and AlgorithmsDigital SwitchingSystemVerilogField-Programmable Gate Arrays (FPGA)VHDLVerilogVery-Large-Scale Integration (VLSI)EDA

About

Digital Design Engineer with more than 7.5 years experience in microarchitecture development, RTL Design, functional specification creation, logic synthesis, timing closure, functional coverage, CDC, code coverage & assertion based verification.

Experience

7 yrs 9 mos
Total Experience
1 yr 6 mos
Average Tenure
--
Current Experience

Ibm

CPU Logic Design Engineer

Sep 2025 – Mar 2026 · 6 mos

  • Specialised in Microarchitecture and RTL Design.
  • Working on current-generation IBM Power and Z processors.
MicroarchitectureRTL Design

Juniper networks

ASIC Design Engineer

Sep 2022 – Sep 2025 · 3 yrs · Bengaluru, Karnataka, India · On-site

  • Working on microarchitecture development, RTL design, lint, synthesis, assertion based verification, code coverage, functional coverage
Microarchitecture developmentRTL designLintSynthesisAssertion based verificationCode coverage+3

Wsaudiology

Digital IC Specialist

Jul 2021 – Aug 2022 · 1 yr 1 mo · Copenhagen, Capital Region, Denmark

Juniper networks

ASIC Design Engineer

Sep 2018 – Oct 2020 · 2 yrs 1 mo · Bengaluru Area, India

  • Microarchitecture Development, RTL Design, Logic Synthesis.
  • Working closely with Verification(microarchitecture-corner cases & testcases) and Physical Design Counterparts.
Microarchitecture DevelopmentRTL DesignLogic SynthesisMicroarchitecture

Mediatek

Engineer

Jul 2017 – Aug 2018 · 1 yr 1 mo · Bengaluru Area, India

Education

Indian Institute of Technology, Bombay

Master's degree — Electronics Systems(VLSI)

Jan 2015 – Jan 2017

National Institute of Technology Calicut

Bachelor's degree

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