Vuong Nguyen

Software Engineer

Sunnyvale, California, United States9 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in MBIST lifecycle management.
Proficient in SCAN architecture and insertion.
Strong background in DFT for high-performance silicon.

Stackforce AI infers this person is a DFT Engineer with expertise in semiconductor testing and verification.

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Skills

Core Skills

MbistGate Level SimulationDftScan ImplementationScan Insertion

Other Skills

Synopsys SMS6Shell ScriptingLogic BISTBoundary ScanDesign Rule Checking (DRC)Coverage AnalysisAutomatic Test Pattern Generation (ATPG)Synopsys toolsMentor GraphicsSemiconductors

About

DFT experience: - 2.5D, 3DIC DFT testing compliance 1838 standard - MBIST insertion, verification, repair, SMART - SCAN architecture and insertion (OCC, compression), LBIST, wrapper, 1687, 1149, testpoint insertion, coverage improve - ATPG (stuckat, transition), simulation (nodelay, delay), tester pattern - DFT timing constraints - EDA: TestMax Manager-DFT-ATPG, Formality, VCS, Primetime, NCverilog, Tessent - Script: Cshell, Tcl, Awk

Experience

9 yrs 8 mos

Total Experience

2 yrs 8 mos

Average Tenure

1 yr 8 mos

Current Experience

Cisco

DFT Engineer

Oct 2024 – Present · 1 yr 8 mos · San Jose, California, United States

Work end-to-end MBIST lifecycle for flagship Cisco NPU silicon. Responsible for MBIST architecture, insertion, verification, timing closure collaboration, Silicon bring up, production yield debug.

MbistSynopsys SMS6

Synopsys inc

3 roles

Staff DFT Solutions Engineer

Feb 2024 – Sep 2024 · 7 mos

Gate Level SimulationShell Scripting

Senior 3DIC DFT Solutions Engineer

Oct 2022 – Feb 2024 · 1 yr 4 mos

1838 3DIC solutions

Gate Level SimulationShell Scripting

DFT engineer

Jun 2020 – Sep 2022 · 2 yrs 3 mos

DFT leader for an IP level product: High Bandwidth Interface (HBI).
Conducting all DFT tasks: architecture, SCAN implementation, equivalent checking, ATPG, simulation (nodelay, with delay), DFT SDC creation, documentation and customer support.
Building DFT flow for my team and join recruitment, training new member.

Gate Level SimulationShell ScriptingDFT

V-silicon technology vietnam

Senior DFT Engineer

Aug 2019 – Jun 2020 · 10 mos · Vietnam

V-silicon is a startup company, moving to here is my challenge in career path. In here, I conducted SCAN implementation (scan chain, compression) for ASIC product. I worked close to RTL design and PnR to solve any problem during development.
But the project was stopped due to company strategy's changed and I felt it don't fit to me any more...

Gate Level SimulationShell ScriptingSCAN implementation

Renesas electronics

Senior DFT Engineer

Jul 2016 – Jul 2019 · 3 yrs · Vietnam

I joined and T.O 7 projects during more 2.5 years working in here with high output quality and on-time schedule. I was promoted to level II Engineer after 2 year working by high performance.
Below are what I did in Renesas:
BSCAN verification & tester pattern making (all PASSED in ATE)
SCAN insertion (scan chain, compression), LBIST insertion & ATPG
Analyze and improve coverage ( stuck-at, transition)
SCAN tester pattern making (all PASSED in ATE)
Timing back-annotation simulation

Gate Level SimulationShell ScriptingSCAN insertion