P

Pooja Gautam

Product Engineer

United Kingdom8 yrs 7 mos experience

Key Highlights

  • 8+ years in ASIC design verification.
  • Expert in UVM and System Verilog.
  • Proficient in multiple communication protocols.
Stackforce AI infers this person is a Semiconductor and Telecommunications expert with a focus on ASIC design verification.

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Skills

Core Skills

Asic Design VerificationFunctional Verification

Other Skills

Functional CoverageSystem Verilog AssertionsVerification EnvironmentUVMSystem VerilogGate Level SimulationDebuggingCross-functional Team LeadershipCode CoveragePerl ScriptingTest PlanningApplication-Specific Integrated Circuits (ASIC) Design VerificationUniversal Verification Methodology (UVM)SystemVerilog

About

Welcome to my profile! I am a dedicated 8+ years of Design Verification Engineer with a specialized focus on ASIC design verification. I boast expertise in System Verilog, UVM, and various communication protocols, including Ethernet, I2C, SPI, AHB Lite, APB, and AXI and Power Management. My foundational education at Motilal Nehru National Institute of Technology, Allahabad, has equipped me with robust theoretical and practical skills that I continuously apply in my professional pursuits. As a Design Verification Engineer, I have developed deep expertise in verification methodologies like UVM, where I excel at building and maintaining test benches and verification environments. This expertise is complemented by my proficiency in System Verilog and Verilog, which I utilize to ensure precise and scalable ASIC designs. My technical acumen extends to work on complex test benches, creating comprehensive test cases, and achieving stringent code and functional coverage targets.I am also skilled in the practical application of protocols such as Ethernet, AHB Lite, and AMBA AHB, AXI , SPI , I2C which are critical to ensuring thorough design verification and compliance with technical specifications. My role often involves meticulous debugging and the preparation of detailed test plans, which are essential for successfully verifying projects. Additionally, I have exposure to gate-level simulation (GLS) for subsystem, enhancing the reliability and performance of final products. I am enthusiastic about continuous learning and applying my skills to innovative projects in the tech industry. I look forward to connecting with like-minded professionals and exploring potential collaborations. Thank you for visiting my profile and considering the value I can bring to your team. ➕More Facts: 🔍Having good communication and problem solving skill. 🔍Ability to work in a dynamic environment. 🔍Believes in progressive learning and possess learning attitude. Contact Info:- E-mail_ID:-poojakumari91996@gmail.com

Experience

8 yrs 7 mos
Total Experience
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Average Tenure
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Current Experience

Arm

Senior Design Verification Engineer

Apr 2026Present · 2 mos · Cambridge, England, United Kingdom · On-site

Synopsys inc

Sr Staff Engineer

Aug 2025Mar 2026 · 7 mos · Bengaluru, Karnataka, India

7rays semiconductors

Lead Engineer-Design Verification

Jan 2025Jul 2025 · 6 mos · Bengaluru, Karnataka, India

Amd

Sr. Silicon design engineer

Jan 2022Dec 2024 · 2 yrs 11 mos · Bengaluru, Karnataka, India

  •  Developed and verified the multiple features for next-generation server variants.
  •  Enhanced test benches for Data Fabric Power Management.
  •  Increased the pass rate of multiple variants through targeted verification issue resolution and RTL problem-solving.
  •  Collaborated on the development of server projects related to Data Fabric Power Management.
  •  Implemented Functional Coverage and System Verilog Assertions across various server variants.
Functional CoverageSystem Verilog AssertionsVerification EnvironmentASIC Design VerificationFunctional Verification

Synopsys inc

ASIC Design Engineer

Sep 2019Jan 2022 · 2 yrs 4 mos · Greater Bengaluru Area

  •  Verified the Policing Counter feature within the EQOS segment of Ethernet.
  •  Authored and verified the Link fault and Minimum interface gap features for XGMAC of Ethernet.
  •  Adapted the UVM test bench and verified the Automotive safety feature for EQOS of Ethernet.
  •  Formulated and executed the verification plan for multiple XGMAC/EQOS features.
  •  Developed and verified test cases, added functional coverage, and SystemVerilog Assertions for numerous features of XGMAC/EQOS.
  •  Troubleshot and resolved failing test cases across various XGMAC/EQOS features.
UVMSystem VerilogFunctional CoverageASIC Design VerificationFunctional Verification

Harman connected services corp india private ltd

Verification Engineer

Jun 2018Sep 2019 · 1 yr 3 mos · Bengaluru, Karnataka, India

  • Verified register functionalities using RAL Block and developed the Security Block within the Polaris project (5G Modem).
  •  Conducted Gate Level Simulation and verification of the Perss Block with Standard Delay Format (SDF) in the Polaris project.
  •  Verified the functionality of the BPSS (built-in self-repair) block using test sequences in the Polaris project.
  •  Authored and validated test cases for diverse features within Polaris and debugged failing test cases.
Gate Level SimulationDebugging

Eximius design

Verification Engineer

Jul 2017May 2018 · 10 mos · Bengaluru, Karnataka, India

  •  Led the verification of the I2C slave block in the Xanadu Project, a multi-master, multi-slave serial computer bus.
  •  Created a comprehensive Verification Plan for the I2C slave block.
  •  Conducted basic functionality tests, register access tests, and connectivity tests (SRAM, OTP, Timers, Register File) for the I2C slave.
  •  Troubleshot and resolved failing test cases for the I2C slave block.

Cetpa infotech pvt. ltd.

Summer Training

May 2015Jun 2015 · 1 mo · Noida, Uttar Pradesh, India

  • The elevator controller system is one of the important aspects in electronics control module in automotive application.First the elevator control system is implemented for multi-storage building.The implementation is based on FPGA based Fuzzy logic controller for intelligent control of elevator group system.This proposed approach is based on algorithm which is developed to reduce the amount of computation required by focusing only on relevant rules and ignoring those which are irrelevant to the condition for better performance for elevator system.Here I have designed for four elevator group.

Education

Motilal Nehru National Institute Of Technology

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 2013Jan 2017

Maharani Laxmi Bai Memorial Inter College

Intermediate (Class 12)

Jan 2010Jan 2012

Maharani Laxmi Bai Memorial Inter College

High School (Class 10) — Science

Jan 2008Jan 2010

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