Menaka Chandramohan

CEO

Toronto, Ontario, Canada21 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Experienced in leading R&D teams in semiconductor design.
Strong expertise in ASIC and mixed signal circuit design.
Proficient in multiple programming languages including C++ and Verilog.

Stackforce AI infers this person is a semiconductor R&D leader with extensive experience in ASIC design and analog circuit engineering.

Contact

Skills

Core Skills

SemiconductorsAsic

Other Skills

RFVerilogTCLAnalogMixed SignalAnalog Circuit DesignCMOSDebuggingCircuit DesignVHDLWirelessSpectrum AnalyzerC++Application-Specific Integrated Circuits (ASIC)

Experience

21 yrs 1 mo

Total Experience

7 yrs

Average Tenure

18 yrs 1 mo

Current Experience

Synopsys inc

5 roles

R&D Engineering, Sr Director

Promoted

May 2026 – Present · 1 mo

RFSemiconductorsVerilogASICTCLAnalog+10

R&D Engineering, Sr Architect

Mar 2024 – Apr 2026 · 2 yrs 1 mo

Sr. Manager R&D

Promoted

Dec 2021 – Mar 2024 · 2 yrs 3 mos

Manager Analog and Mixed Signal Layout Design

Apr 2018 – Dec 2021 · 3 yrs 8 mos

R&D Engineer

Apr 2008 – Apr 2018 · 10 yrs

Snowbush microelectronics

Physical Layout Engineer at Snowbush

Jan 2006 – Jan 2007 · 1 yr

Rohde and schwarz

2 roles

Technical Support Engineer

Jan 2004 – Jan 2006 · 2 yrs

Product Manager

Jan 2004 – Jan 2006 · 2 yrs

Education

The George Washington University

Jan 2002 – Jan 2004

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