Ujjwal Rakesh

Software Engineer

Patna, Bihar, India2 yrs 7 mos experience

Key Highlights

Led a $2.4M defense project
Published multiple research papers
Expertise in RF and microwave systems

Stackforce AI infers this person is a Semiconductor and RF Engineering specialist with strong project management skills.

Contact

Skills

Core Skills

Rf EngineeringProject ManagementRtl DesignResearchDigital Design

Other Skills

RFMW Coaxial cablesFilter DesignQuestaSimSystem VerilogResearch SkillsMicrosoft WordVerilogLTSpiceCygwinMIPS Instruction SetDC HarnessBill of Materials (BOM) ManagementTechnical DocumentationMIL-STD-810

Experience

2 yrs 7 mos

Total Experience

Average Tenure

Current Experience

Nkrf products & services

Technical Engineer

Apr 2024 – Feb 2026 · 1 yr 10 mos · Bengaluru, Karnataka, India · On-site

Led a critical project worth $2.4M for DRDO- CEMILAC qualification of airborne systems, ensuring MIL-STD criteria.
Developed expertise in RF/microwave cables and DC harnessing, researching various wideband cable types, connectors (e.g., D38999, BMA, TNC, SMA), and filters used in defence and aerospace applications

RFMW Coaxial cablesFilter DesignRF EngineeringProject Management

Alpha semiconductors

RTL Design Intern

Mar 2024 – Apr 2024 · 1 mo · Bengaluru, Karnataka, India · Remote

Worked on MIPS cores instructions and CPU 5-stage pipelining, coded a wrapper for ALU and ROM modules for Load and Store operations. Integrated code while using Cygwin and Questasim, learned debugging skills.

QuestaSimSystem VerilogRTL Design

Ieee communications society

Undergraduate Researcher

Jun 2023 – Mar 2024 · 9 mos

Researched on different topics and managed to publish 3 papers and 2 newsletters under IEEE COMSOC Society

Research SkillsMicrosoft WordResearch

Signalchip innovations

Digital Design Intern

Dec 2022 – Jan 2023 · 1 mo · Bengaluru, Karnataka, India · Remote

Discovered and worked on various projects such as implementing 5 point Moving Average Filter and then worked on implementing LPF and ADC through LT Spice software. Implemented CPU scheduling based on TDMA using Round Robin Arbiter.

VerilogLTSpiceDigital Design