Ajay Balu Kuzhively — Product Engineer
Engineer specializing in Digital VLSI design, actively seeking full-time opportunities in the field of Digital/Hardware/SoC/ASIC or Physical design. I have experience in Python, UNIX, Perl, BASH, and TCL scripting. Currently Working as a Stdcell Characterization Engineer at Qualcomm, San Diego. -->3nm Standard cell Tech lead for TSMC foundry. Successfully taped out chips for 0.9 PDK, 1.0 PDK, and 1.1 PDK by defining methodology/modeling changes and aligning with the foundry, tool vendor, and internal teams. -->Owner of Slew and load methodology deliverables for all library characterizations. Reduced the deliverable time by 60% (reduced run time with an end-to-end script written in Python). Analysis of Standard cells, layout, and methodologies to improve PPA. -->Methodology alignment, spec creation, review, and debugging for MC vs LVF reports, Voltage scaling reports, MIS reports, and CLS Reports. -->Developed Cell models for new and existing Standard cells. Performed functional and formal verification for new and existing standard cells. -->Collaborated closely with cross-functional teams to address library cell issues, sigma variation analysis, and quality control. Enhanced existing methodologies to improve timing, power, area, and reliability. MS Thesis on Quantization and Evaluation of AI Algorithms for Hardware Acceleration. o A low-precision sparse DNN model was developed for the reconstruction of the image. o Binarize a part of the layers to decrease the number of weights and activations on the chip to improve the accuracy. o Reclaiming the accuracy for more complex datasets with layer-wise quantization. Selected Coursework: - VLSI design - Computer Architecture 2 - Neuromorphic Computing and Hardware Design - Hardware Acceleration and FPGA Computing - Constructionist approach for Microprocessor Design - Digital Signals and Circuits - Analog Integrated Circuits - Advanced Analog Integrated Circuits
Stackforce AI infers this person is a Semiconductor and Hardware Acceleration expert with strong software development skills.
Location: Chandler, Arizona, United States
Experience: 5 yrs 3 mos
Skills
- Physical Design
- Timing Verification
- Standard Cell Characterization
- Methodology Development
- Hardware Acceleration
- Model Verification
- Software Development
- Automation
Career Highlights
- Led 3nm standard cell characterization at Qualcomm.
- Reduced deliverable time by 60% using Python scripting.
- Successfully signed off multiple test chip tapeouts at Intel.
Work Experience
Intel Corporation
Physical Design Engineer (2 yrs 3 mos)
Qualcomm
Engineer (2 yrs 1 mo)
Arizona State University
Graduate Research Assistant (9 mos)
Tally Solutions Pvt Ltd
Software Developer (11 mos)
Education
Master of Science - MS at Arizona State University
B.Tech at National Institute of Technology Calicut