Ramakrishna Uppalapati — CEO

Expert in ASIC Digital Design focused on High-Speed SerDes IP, specializing in 128G PAM4 and NRZ signaling. Currently leading a team of highly motivated engineers across Firmware, ASIC RTL, and FPGA Validation, driving the delivery of complex silicon IPs from architecture to hardware-ready status. Bringing vast experience in high-speed serial interfaces and the strategic oversight of cross-functional teams to solve critical timing, signal integrity, and integration challenges in advanced FinFET nodes. Leading a team of talented engineers in the ASIC Digital Design of High-Speed SerDes IP, supporting both 128G PAM4 and NRZ modulation schemes. • Overseeing a multi-disciplinary group across Firmware, ASIC RTL, and FPGA Validation to ensure robust, high-throughput IP delivery. • Directing the digital architecture for next-generation SerDes, leveraging vast experience in PCS, PMA, and complex clocking architectures to ensure first-pass silicon success. • Managing pre- and post-silicon validation of Gigabit Transceiver blocks on advanced nodes, including Xilinx 7nm and Everest platforms. • Driving signal integrity analysis for 128G interfaces, utilizing DFE/CTLE tuning and jitter analysis with high-speed measurement equipment. Architecting and developing the "LiteFast" lightweight high-speed serial protocol on Microsemi FPGA platforms. • Implementing various transceiver-related protocols such as SATA, JESD204B, XAUI, and high-performance Video Algorithms. • Advanced expertise in Static Timing Analysis (STA) and Clock Domain Crossing (CDC) issues, providing scalable solutions for complex SoC designs. • Leading the validation of Gigabit transceivers over various protocols (SDI, XAUI, SATA) using high-speed scopes and BERT equipment.

Stackforce AI infers this person is a leader in ASIC Digital Design with a focus on high-speed serial interfaces.

Location: Hyderabad, Telangana, India

Experience: 13 yrs 1 mo