Shyam Razesh Ambati — Software Engineer
Physical Design Engineer with 2 years of experience in block-level, top-level physical design. Hands-on expertise in PnR, STA, timing closure, and signoff (STA, DRC, LVS). Familiar with multiple technology nodes, including 7nm, 16nm, 28nm, 32nm, and 90nm, using Synopsys and Cadence tools. A quick learner eager to take on more responsibility and grow into a senior role. Actively exploring global opportunities in ASIC Physical Design.
Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in ASIC design.
Location: Bengaluru, Karnataka, India
Experience: 1 yr 2 mos
Skills
- Physical Design
- Static Timing Analysis
Career Highlights
- Hands-on expertise in physical design and timing closure.
- Experience with multiple technology nodes from 7nm to 90nm.
- Eager to grow into a senior role in ASIC Physical Design.
Work Experience
AndGate Informatics Pvt. Ltd.
Physical Design Engineer (2 mos)
Siliconus Technologies Pvt Ltd
Physical Design Engineer (1 yr)
Physical Design Engineer (5 mos)
Maven Silicon
Advanced Physical Design and Verification Trainee (7 mos)
Advanced Level Telecom Training Center (ALTTC)
TELECOM TECHNOLOGIES AND NETWORK (1 mo)
Education
Bachelor of Technology - BTech at Gayatri Vidya Parishad College of Engineering (Autonomous)