Shyam Razesh Ambati

Software Engineer

Bengaluru, Karnataka, India1 yr 2 mos experience

Key Highlights

  • Hands-on expertise in physical design and timing closure.
  • Experience with multiple technology nodes from 7nm to 90nm.
  • Eager to grow into a senior role in ASIC Physical Design.
Stackforce AI infers this person is a Semiconductor Physical Design Engineer with expertise in ASIC design.

Contact

Skills

Core Skills

Physical DesignStatic Timing Analysis

Other Skills

Fusion compilerGenusLinuxPacket TracerICC2Design compilerPrime TimeInnovusTempusVoltusEM & IRPhysical VerificationPhysical Design AlgorithmsTCLCalibre

About

Physical Design Engineer with 2 years of experience in block-level, top-level physical design. Hands-on expertise in PnR, STA, timing closure, and signoff (STA, DRC, LVS). Familiar with multiple technology nodes, including 7nm, 16nm, 28nm, 32nm, and 90nm, using Synopsys and Cadence tools. A quick learner eager to take on more responsibility and grow into a senior role. Actively exploring global opportunities in ASIC Physical Design.

Experience

1 yr 2 mos
Total Experience
1 yr
Average Tenure
2 mos
Current Experience

Andgate informatics pvt. ltd.

Physical Design Engineer

Apr 2026Present · 2 mos · Noida · Remote

Siliconus technologies pvt ltd

2 roles

Physical Design Engineer

Nov 2024Nov 2025 · 1 yr · On-site

Fusion compilerGenusPhysical Design

Physical Design Engineer

May 2024Oct 2024 · 5 mos · On-site

LinuxStatic Timing Analysis

Maven silicon

Advanced Physical Design and Verification Trainee

Jul 2023Feb 2024 · 7 mos · Bengaluru, Karnataka, India · On-site

  • As a Trainee in Physical Design, I have played a crucial role in learning and contributing to the design and layout of integrated circuits. I have worked closely with experienced physical design engineers, gaining hands-on experience and enhancing my skills in various aspects of the physical design process.
  • Hands-on experience in RTL to GDSII of Integrated circuit design of SOC.
LinuxStatic Timing AnalysisPhysical Design

Advanced level telecom training center (alttc)

TELECOM TECHNOLOGIES AND NETWORK

Feb 2023Mar 2023 · 1 mo · Ghaziabad, Uttar Pradesh, India · Remote

Packet Tracer

Education

Gayatri Vidya Parishad College of Engineering (Autonomous)

Bachelor of Technology - BTech

Aug 2019Apr 2023

Stackforce found 100+ more professionals with Physical Design & Static Timing Analysis

Explore similar profiles based on matching skills and experience