Subhash Padamata

Software Engineer

Bhimavaram, Andhra Pradesh, India1 yr 4 mos experience

Key Highlights

Expert in formal verification of RTL designs.
Proficient in SystemVerilog Assertions and JasperGold.
Strong debugging skills in complex verification environments.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in formal methods and RTL design.

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Skills

Core Skills

Formal VerificationSystemverilog

Other Skills

systemverilog assertionJasperGoldTCL scriptingDebuggingSystemVerilog AssertionsCoverage AnalysisVerilogcadence jaspergoldSynopsys toolsAssessmentSemiconductor IndustryAnalytical WritingService StandardsHands-on TrainingDistributed Computing

About

Formal verification Engineer at metavlsi technologies

Experience

1 yr 4 mos

Total Experience

1 yr 4 mos

Average Tenure

1 yr 4 mos

Current Experience

Metavlsi

Formal verification engineer

Feb 2025 – Present · 1 yr 4 mos · Bengaluru, Karnataka, India · On-site

Working on formal verification of RTL designs using SystemVerilog Assertions (SVA) and industry-standard FV tools.
Developing assertions, assumptions, and coverage models for protocol and functional verification.
Experience in verifying FIFO, APB, watchdog timer, MMU, ID mapping, and serial receiver designs.
Performing property checking, reachability analysis, invariant verification, and debugging counterexamples.
Working with constrained formal environments to improve convergence and reduce state-space complexity.
Skilled in debugging assertion failures, dead code, and coverage closure issues.
Hands-on experience with JasperGold, TCL scripting, and RTL debugging.
Collaborating with design and verification teams to ensure functional correctness and verification completeness.