Nalla Bhanuvardhan Reddy — Software Engineer
I am a Design Verification Engineer with 3 years of experience in digital electronics and a sounding Knowledge in Verilog, System Verilog, and UVM. My expertise lies in building reusable System Verilog-based test benches, developing UVM-based verification components, and writing coverage and assertions. I have a good understanding of RTL design and verification using System Verilog, as well as IP-level understanding of test bench and verification environments using UVM. I am skilled in using standard protocols such as APB and AHB. Additionally, I have experience working with simulation tools like Synopsys VCS and VERDI.
Stackforce AI infers this person is a Design Verification Engineer specializing in digital electronics and verification methodologies.
Location: Hyderabad, Telangana, India
Experience: 5 yrs 11 mos
Skills
- Assertion Based Verification
- Universal Verification Methodology (uvm)
Career Highlights
- 3 years of experience in digital electronics.
- Expertise in System Verilog and UVM-based test benches.
- Proficient in using Synopsys VCS and VERDI simulation tools.
Work Experience
OTSI - Object Technology Solutions Inc.
Design Verification Engineer (2 yrs 10 mos)
Cerium Systems
Design Verification Engineer (1 yr)
Vertex Electronics Hyderabad
Verification Engineer (2 yrs 1 mo)
Education
Bachelor of Engineering - BE at Osmania University
Diploma of Education at Government Polytechnic College