Pradeep Reddy Gujjula — Product Engineer

Senior ASIC Design Verification Engineer at Synopsys, with strong hands-on experience in functional verification of complex digital IPs and SoCs using SystemVerilog, UVM, and assertion-based verification (SVA). Proven ability to build, enhance, and debug scalable verification environments focused on coverage closure, corner-case detection, and pre-silicon bug identification. Actively involved in developing assertion frameworks, performing functional and code coverage analysis, and supporting simulation and formal verification flows to ensure robust and silicon-ready designs. Experienced in debugging complex RTL issues through close collaboration with design, architecture, and validation teams, contributing to high-quality, industry-grade semiconductor solutions. Pursuing an M.Tech in VLSI from BITS Pilani and holds a B.Tech in Electronics, combining strong academic fundamentals with real-world DV expertise. Motivated by solving challenging verification problems and driving efficient, reliable, and scalable verification methodologies for next-generation semiconductor products.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in digital design and verification methodologies.

Location: Hyderabad, Telangana, India

Experience: 3 yrs 5 mos